cleared then re-enabling the NOR gate causes another low-high
transition on the INT2 line and another interrupt is generated. The
interrupt handler is then called again and the process is repeated
until there are no further interrupts on ATNRQ2*. Thus multiple
interrupt sources can share an ATNRQ* level.
The STEbus variant of the board is capable of generating an
interrupt out onto the STEbus in all its STEbus operating modes by
writing 1 to General Control Register 0 bit 2. The ATNRQ* level that
is asserted is set up on link LK6. If the board is in STEbus slave mode
then this interrupt out is cleared by a write access to the mailbox
area of DPR from an STEbus master.
Note that the STEbus board variants can only drive or receive
interrupts on STEbus ATNRQ0*, ATNRQ1*, ATNRQ2* or
ATNRQ3*. ATNRQ4-7* are not connected to the board.
The diagram over the page shows how the INTx pins of the 386EX
processor relate to the interrupt request (IR) numbers used by the
interrupt controller.
J539 TARGET386EX
2192-08270-000-000
Section 4. Using the TARGET386EX
Page 24
Interrupt Control Unit
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