Memory Map After Power-up/Reset
After reset the upper chip select UCS is enabled with the entire
64MB memory address space as its address block. This allows the
boot monitor program to run from the top of memory. By default
the monitor program will run in real mode, the UCS register is then
programmed by the monitor software to assert the Flash ROM chip
select at addresses from 80000h to FFFFFh (512KB).
The state of LK19 tells the monitor whether to run itself or the users
application code. Application code must always start running from
address 80000h (bottom of Flash ROM). Having the Flash ROM
occupy this much of the memory map may obscure areas of the
memory map required by PC/104 or STEbus peripheral boards. If
this is the case then the application code can be written to re-
program the start address of UCS, while it is running to effectively
limit the size of the Flash ROM. Code should be written to jump into
the reduced Flash ROM area and then to re-program UCS for the
new size.
Memory space between the bottom of ROM and the top of main
RAM (location selected by CS0) will be automatically mapped to the
default expansion bus (STEbus or PC/104 depending on bit 2 of
General Control Register 1). CS3-6 can be programmed to direct
accesses to the non-default bus. CS1 decodes the on-board address
of the 16/32KB Dual Port RAM, this is fully re-locatable.
Note: when running the monitor software on 512KB RAM variants
of board the extra 256KB of RAM is not accessible until chip select
CS0 is re-programmed because in order to gain access to STEbus or
PC/104 bus or the on-board DPR located by CS1, either the bottom
of the Flash ROM area must be moved up the memory map by
programming UCS or the top of the on-board main RAM must be
moved down by programming CS0.
2192-08270-000-000
Section 4. Using the TARGET386EX
J539 TARGET386EX
Page 19
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