Analog Devices VISUALDSP++ 3.5, Manual

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ADSP-219x DSP Booting
3-12 Vi+ Loader Manual
for 16-Bit Processors
Serial EPROM Booting
The SPI0 port is used when booting from an SPI-compatible EPROM.
The SPI port selects a single serial EPROM device using the
PF0
pin as a
chip select, submits a read command and address
0x00
, and begins to
clock consecutive data into memory (internal memory or external mem-
ory) at a
SCK
clock frequency of HCLK/60. The DSP streams the
complete boot image in and processes it without further handshake with
the SPI EPROM.
Two types of SPI EEPROM devices are supported: devices of 4K bytes
and smaller (12-bit address range), and those larger than 4K bytes (16-bit
address range). The SPI boot stream may not exceed 64 kilobytes.
This boot operation is controlled by an SPI boot routine in internal ROM
space. While booting via serial EPROM, the highest 16 locations in
page 0 program memory block (
0x7FF0
to
0x7FFF
) and the top 272 loca-
tions of page 0 data memory block (
0xFEF0
to
0xFFFF
) are reserved for use
by the ROM boot routine. Refer to the Application Note EE-145 for SPI
booting examples.
No-booting
When
BMODE2-0
is strapped to a
000
or
001
, the ADSP-219x DSP comes
out of hardware reset and begins to execute code from page 1 memory
space (
0x01 0000
). The specified packing mode depends on the state of
the
BMODE0
pin (
0
= 8-bit
ext
/24-bit
int
,
1
= 16-bit
ext
/24-bit
int
). By
default, the External Port Interface (EPI) is configured to operate with the
divide-by-128 clock and a read wait-state count of 7.
!
No-boot mode does not use boot-stream format.
After reset, the DSP starts program execution from external address
0x010000
. When the no-boot option is selected, the DSP typically expects
an 8- or 16-bit EPROM or Flash device connected to the memory strobe