Analog Devices VISUALDSP++ 3.5, Manual, Page: 44 / 166

Blackfin Processor Booting
2-14 Vi+ Loader Manual
for 16-Bit Processors
"
Bank 2 (
0x1000 0000
)
"
Bank 3 (
0x1800 0000
)
!
SDRAM must be initialized by user code before any instructions or
data are loaded into it.
For more information see “Using Second-Stage Loader” on page 2-49 .
Second-Stage Loader Restrictions
When using the second-stage loader:
• The bottom of L2 memory must be reserved during booting. These
locations can be reallocated during runtime. The following loca-
tions pertain to the current second-stage loaders.
"
For 8- and 16-bit PROM/Flash booting, reserve
0xF003 FE00–0xF003 FFFF
(last 512 bytes).
"
For 8- and 16-bit addressable SPI booting, reserve
0xF003 FD00–0xF003 FFFF
(last 768 bytes).
• If segments reside in SDRAM memory, configure the SDRAM reg-
isters accordingly in the second-stage loader kernels before booting.
"
Modify section of code called “
SDRAM setup
” in the
second-stage loader and rebuild the second-stage loader.
• Any segments residing in L1 instruction memory
(
0xFFA0 0000–0xFFA0 3FFF
) must be 8-byte aligned.
"
Declare segments, within the .
LDF
file, that reside in L1
instruction memory at starting locations that are 8-byte
aligned (for example,
0xFFA0 0000
,
0xFFA0 0008
,
0xFFA0 0010
, and so on).
"
Or use the
.ALIGN 8;
directives in the application code.