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Blackfin Processor Booting

2-16

Vi+ Loader Manual

for 16-Bit Processors

ADSP-BF531/BF532/BF533 Processor Booting

Upon reset, an ADSP-BF531/BF532/BF533 processor jumps to the
on-chip boot ROM (if

BMODE = 01

) or jumps to 16-bit external mem-

ory for execution (if

BMODE = 00

) located at

0xEF00 0000

Table 2-2

shows

booting modes and execution start addresses for ADSP-BF531,
ADSP-BF532, and ADSP-BF533 processors.

A description of each boot mode is as follows.

•

“ADSP-BF531/BF532/BF533 Processor On-Chip Boot ROM” on
page 2-17

•

“ADSP-BF531/BF532/BF533 Processor Boot Streams” on
page 2-19

Table 2-2. ADSP-BF531/BF532/BF533 Processor Boot Mode Selections

Boot Source

BMODE[1:0]

Execution Start Address

ADSP-BF531
ADSP-BF532

Processors

ADSP-BF533

Processor

Execute from 16-bit External ASYNC Bank0
memory (no-boot mode or bypass on-chip boot
ROM)

0x2000 0000

Boot from 8- or 16-bit Prom/Flash

0xFFA0 8000

0xFFA0 0000

Reserved

0xFFA0 8000

0xFFA0 0000

Boot from a 8-, 16-, or 24-bit addressable SPI
memory

0xFFA0 8000

0xFFA0 0000

Summary of Contents for VISUALDSP++ 3.5

Page 1: ...W 3 5 Loader Manual for 16 Bit Processors Revision 1 0 October 2003 Part Number 82 000035 04 Analog Devices Inc One Technology Way Norwood Mass 02062 9106 a ...

Page 2: ...sumed by Analog Devices for its use nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by impli cation or otherwise under the patent rights of Analog Devices Inc Trademark and Service Mark Notice The Analog Devices logo VisualDSP the VisualDSP logo Blackfin the Blackfin logo CROSSCORE the CROSSCORE logo and EZ KIT Lite are regis...

Page 3: ...port xii Supported Processors xiii Product Information xiii MyAnalog com xiv Embedded Processor and DSP Product Information xiv Related Documents xv Online Technical Documentation xv From VisualDSP xvi From Windows xvi From the Web xvii Printed Manuals xvii VisualDSP Documentation Set xvii Hardware Manuals xviii Datasheets xviii Contacting DSP Publications xviii ...

Page 4: ...s 1 4 Booting Modes 1 5 No boot Mode 1 5 PROM Booting Mode 1 6 Host Booting Mode 1 6 Boot Kernels 1 7 Loader Tasks 1 8 Loader Files 1 8 File Searches 1 9 BLACKFIN PROCESSOR LOADER SPLITTER Blackfin Processor Booting 2 2 ADSP BF535 Processor Booting 2 3 ADSP BF535 Processor On Chip Boot ROM 2 4 ADSP BF535 Processor Second Stage Loader 2 6 ADSP BF535 Processor Boot Streams 2 8 Output Loader Files 2 ...

Page 5: ...Initialization Blocks 2 21 ADSP BF531 BF532 BF533 Processor Memory Ranges 2 25 ADSP BF531 BF532 BF533 Processor SPl Memory Boot Sequence 2 26 ADSP BF561 Processor Booting 2 28 ADSP BF561 Processor Boot Streams 2 29 ADSP BF561 Processor Memory Ranges 2 34 ADSP BF561 Processor Initialization Blocks 2 35 ADSP BF561 Multiple DXE Booting 2 36 ADSP BF531 BF532 BF533 and ADSP BF561 Multiple DXE Booting 2...

Page 6: ...9x DSP Boot Kernel 3 4 ADSP 219x DSP Boot Streams 3 4 Parallel EPROM Boot Streams 3 4 Block Headers 3 5 Data Blocks 3 6 ADSP 219x DSP Multiple DXE Support 3 7 Host Booting 3 10 UART Booting 3 11 Serial EPROM Booting 3 12 No booting 3 12 Enriching Boot EPROMs with No boot Data 3 16 ADSP 219x DSP Loader Guide 3 19 ADSP 219x Loader Command Line Reference 3 19 File Searches 3 20 File Extensions 3 20 L...

Page 7: ...92 DSP RBTL and Overlays 4 8 Using Overlay Symbols 4 9 ADSP 2192 DSP Loader Guide 4 10 Single Processor Command Line 4 10 Two Processor Command Line 4 11 File Searches 4 12 File Extensions 4 13 Loader Command Line Switches 4 13 ADSP 218X DSP LOADER SPLITTER ADSP 218x DSP Loader Guide 5 1 Boot Modes 5 2 Determining Boot Modes 5 4 EPROM Booting BDMA 5 6 ADSP 218x BDMA Loader Command Line Reference 5...

Page 8: ...ine Reference 5 16 FILE FORMATS Source Files A 2 C C Source Files A 2 Assembly Source Files A 3 Assembly Initialization Data Files A 3 Header Files A 4 Linker Description Files A 4 Linker Command Line Files A 5 Build Files A 5 Assembler Object Files A 5 Library Files A 6 Linker Output Files A 6 Memory Map Files A 7 Loader Output Files in Intel Hex 32 Format A 7 Splitter Output Files in ASCII Forma...

Page 9: ...VisualDSP 3 5 Loader Manual ix for 16 Bit Processors Contents INDEX ...

Page 10: ...x VisualDSP 3 5 Loader Manual for 16 Bit Processors ...

Page 11: ...ADSP 21xx DSPs and Blackfin processors These files are then programmed burned into an external memory device within your target system Intended Audience The primary audience for this manual is DSP programmers who are familiar with Analog Devices DSPs This manual assumes that the audi ence has a working knowledge of the appropriate DSP architecture and instruction set Programmers who are unfamiliar...

Page 12: ...Loader Splitter Appendix A File Formats Technical or Customer Support You can reach DSP Tools Support in the following ways Visit the DSP Development Tools website at www analog com technology dsp developmentTools index html Email questions to dsptools support analog com Phone questions to 1 800 ANALOGD Contact your ADI local sales office or authorized distributor Send questions by mail to Analog ...

Page 13: ... 2196 ADSP 21990 ADSP 21991 and ADSP 21992 The name Blackfin refers to a family of Analog Devices 16 bit embed ded processors VisualDSP currently supports the following Blackfin processors Blackfin Processors ADSP BF531 ADSP BF532 formerly ADSP 21532 ADSP BF533 ADSP BF535 formerly ADSP 21535 ADSP BF561 and AD6532 Product Information You can obtain product information from the Analog Devices Web si...

Page 14: ...s for you to select the information you want to receive If you are already a registered user just log on Your user name is your email address Embedded Processor and DSP Product Information For information on digital signal processors visit our website at www analog com processors which provides access to technical publica tions datasheets application notes product overviews and product announcemen...

Page 15: ...A description of each documentation file type is as follows VisualDSP 3 5 Getting Started Guide for 16 Bit Processors VisualDSP 3 5 User s Guide for 16 Bit Processors VisualDSP 3 5 Product Release Bulletin for 16 Bit Processors VisualDSP 3 5 C C Compiler and Library Manual for Blackfin Processors VisualDSP 3 5 C C Compiler and Library Manual for ADSP 219x DSPs VisualDSP 3 5 C Compiler and Library ...

Page 16: ...ve constructed there are many ways to open VisualDSP online Help or the supplementary documentation from Windows Help system files CHM files are located in the Help folder and PDF files are located in the Docs folder of your VisualDSP installation The Docs folder also contains the Dinkum Abridged C library and FlexLM net work license manager software documentation File Description CHM Help system ...

Page 17: ...the tools manuals point your browser at www analog com technology dsp developmentTools gen_purpose html Select a DSP family and book title Download archive ZIP files one for each manual Use any archive management software such as WinZip to decompress downloaded files Printed Manuals For general questions regarding literature ordering call the Literature Center at 1 800 ANALOGD 1 800 262 5643 and f...

Page 18: ...s can be downloaded from the Analog Devices Web site As a general rule any datasheet with a letter suffix L M N can be obtained from the Literature Center at 1 800 ANALOGD 1 800 262 5643 or downloaded from the Web site Datasheets without the suffix can be downloaded from the Web site only no hard copies are available You can ask for the datasheet by a part name or by product number If you want to ...

Page 19: ...r that this that Optional items in syntax descriptions appear within brackets and sepa rated by vertical bars read the example as an optional this or that this Optional item lists in syntax descriptions appear within brackets delimited by commas and terminated with an ellipsis read the example as an optional comma separated list of this SECTION Commands directives keywords and feature names are in...

Page 20: ...Notation Conventions xx VisualDSP Loader Manual for 16 Bit Processors ...

Page 21: ... of this chapter applies to all 16 bit processors Information applicable to a particular target processor or to a particular processor fam ily is provided in the following chapters Chapter 2 Blackfin Processor Loader Splitter on page 2 1 Chapter 3 ADSP 219x DSP Loader Splitter on page 3 1 Chapter 4 ADSP 2192 12 DSP Loader on page 4 1 Chapter 5 ADSP 218x DSP Loader Splitter on page 5 1 Program Deve...

Page 22: ...ustry standard format for executable files The linker also produces map files and other embedded information used by the debugger DWARF 2 These executable files DXE are not readable by the processor hardware directly They are neither supposed to be burned onto a EPROM or Flash memory device Executable files are consumed by VisualDSP debugging targets such as the simulator or emulator Refer to the ...

Page 23: ...oject Options dialog box in the VisualDSP environment or on the loader s command line Option settings on the Load page corre spond to switches typed on the command line The loader splitter output is either a boot loadable or non bootable file described in the following Boot loadable Files Versus Non bootable Files The output is meant to be loaded onto the target There are sev eral ways to use the ...

Page 24: ...thin your target system The loader outputs files in industry standard file formats such as Intel hex 32 and Motorola S which are readable by most EPROM burners For advanced usage other file formats are supported A non bootable EPROM image file executes from the processor s external memory bypassing the build in boot mechanisms Preparing a non boota ble EPROM image is called splitting In most cases...

Page 25: ...ned by sampling one or more of input flag pins Booting sequences highly processor specific are detailed in the following chapters ADSP 218x ADSP 219x and Blackfin processors support different boot mechanisms Generally spoken the following schemes can be used to pro vide program instructions to the processors after reset No boot Mode PROM Booting Mode Host Booting Mode No boot Mode The processors s...

Page 26: ...res it to file format that can be burned into the PROM Host Booting Mode In this scheme the target processor is slave to a host system After reset the processor delays program execution until it gets signalled by the host system that the boot process has completed Depending on hardware capa bilities there are two different methods of host booting In the first case the host system has full control ...

Page 27: ...kernel then brings the rest of the booting routines into the proces sor s memory Finally the boot kernel overwrites itself with the final block and jumps to the beginning of the application program On the ADSP 219x DSPs the highest 16 locations in page 0 program memory and the highest 272 locations in page 0 data memory are reserved for use by the ROM boot routines typically for setting up DMA dat...

Page 28: ... the LDR file in PROM space Specifying processor IDs for multiple input DXEs for a multipro cessor system Loader Files The loader splitter output is essentially the same executable code as in the input DXE file The loader repackages the executable as illustrated in Figure 1 1 Processor code in a loader file is split into blocks Each code block is marked with a tag that contains information about t...

Page 29: ...the current working directory Overlay and shared memory files the loader recognizes overlay memory files but does not expect these files on the command line Place the files in the same directory as the executable file that refers to them The loader can locate them when processing the executable Figure 1 1 DXE Files versus LDR Files Code Data Symbols Debug Information DXE File Code Data Symbols Deb...

Page 30: ... for 16 Bit Processors When providing an input or output file as a loader splitter command line parameter use the following guidelines Enclose long file names within straight quotes long file name Append the appropriate file extension to each file ...

Page 31: ...ory material applies to all processor families Loader operations specific to ADSP BF5xx Blackfin processors are detailed in the following sections Blackfin Processor Booting on page 2 2 Provides general information on various booting modes including information on second stage kernels ADSP BF535 Processor Booting on page 2 3 ADSP BF531 BF532 BF533 Processor Booting on page 2 16 ADSP BF561 Processo...

Page 32: ...s There is also a no boot option bypass mode in which execu tion occurs from a 16 bit external memory At powerup after the reset the processor transitions into a boot mode sequence configured by the BMODE pins These pins can be read through bits in the System Reset Configuration Register SYSCR The BMODE pins are dedicated mode control pins that is no other functions are shared with these pins Figu...

Page 33: ... description of each boot mode is as follows ADSP BF535 Processor On Chip Boot ROM on page 2 4 ADSP BF535 Processor Second Stage Loader on page 2 6 ADSP BF535 Processor Boot Streams on page 2 8 ADSP BF535 Processor Memory Ranges on page 2 13 Table 2 1 ADSP BF535 Processor Boot Mode Selections Boot Source BMODE 2 0 Execution Start Address Execute from 16 bit external memory Async Bank 0 no boot mod...

Page 34: ... and jump to the start of L2 memory 0xF000 0000 for execution The on chip boot ROM does this by checking bit 4 of the SYSCR If bit 4 is not set the on chip boot ROM performs the full boot sequence If bit 4 is set the on chip boot ROM bypasses the full boot sequence and jumps to 0xF000 0000 The register settings are shown in Figure 2 3 Figure 2 2 ADSP BF535 Processors On Chip Boot ROM ADSP BF535 Pr...

Page 35: ...es can define the size of the actual application code or a second stage loader boot kernel that boots in the application code Figure 2 3 ADSP BF535 Processors System Reset Configuration Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 BMODE 2 0 RO 000 Bypass boot ROM execute from 16 bit wide external memory 001 Use boot ROM to load from 8 bit 16 bit FLASH 010 Use boot ROM to configure and load boo...

Page 36: ...states or hold time cycles for a Flash PROM booting or to change the baud rate for a SPI boot see Command Line Switches on page 2 42 for more infor mation on these features When a second stage loader is used for booting the following sequence takes place 1 Upon RESET the on chip boot ROM downloads N bytes the second stage loader from external memory to address 0xF000 0000 in L2 memory Figure 2 4 F...

Page 37: ...r Figure 2 6 ADSP BF535 Processors Booting Application Code ADSP BF535 Processor 4 Byte Header N 2nd Stage Loader PROM Flash or SPI Device 2nd Stage Loader or Application Code 0x0 L2 Memory 0xF000 0000 0xEF00 0000 On Chip Boot ROM 2nd Stage Loader Application Code Data 2nd Stage Loader ADSP BF535 Processor 4 Byte Header N 2 nd S tage Loader 0x0 Application Code Data A B C PROM Flash or SPI Device ...

Page 38: ...m in such a way that the on chip boot ROM and the second stage loader can correctly load the application code and data to the processor memory Therefore the boot stream contains not only the user application code but also header and flag information that is used by the on chip boot ROM and the second stage loader Figure 2 7 ADSP BF535 Processors Starting Application Code ADSP BF535 Processor 4 Byt...

Page 39: ... are covered as follows Output Loader Files on page 2 9 Global Headers on page 2 12 Block Headers on page 2 13 Flags on page 2 13 Output Loader Files An output loader file for 8 bit PROM Flash booting and 8 16 bit addressable SPI booting without the second stage loader 4 Byte Header for Byte Count N Byte 0 Byte 1 Byte 2 Byte 3 Output LDR File Application Code Byte Count for Application Code D7 D0 ...

Page 40: ...it addressable SPI booting with the second stage loader or kernel 4 Byte Header for Byte Count N Byte 0 Byte 1 Byte 2 Byte 3 Output LDR File Byte Count for 2nd Stage Loader 0x00 0x00 0x00 0x00 0x00 D15 D8 D7 D0 Application Code N words 0x00 0x00 0x00 4 Byte Header for Byte Count N Byte 0 Byte 1 Byte 2 Byte 0 Byte 1 Byte 2 Output LDR File 2nd Stage Loader N Bytes Byte Count for 2nd Stage Loader D7 ...

Page 41: ... a booting process 4 Byte Header for Byte Count N Byte 0 Byte 1 Byte 2 Byte 0 Byte 2 Output LDR File 2nd Stage Loader Byte Count for 2nd Stage Loader 0x00 0x00 0x00 0x00 0x00 Byte 1 Byte 3 Byte 5 D15 D8 D7 D0 Byte 4 Application Code in blocks Byte Count N 2nd Stage Loader 2nd Stage Loader Address Global Header Size of Application Code N1 Application Code Output LDR File Address of the Bottom of L2...

Page 42: ...g A global header for 8 and 16 bit addressable SPI booting Start Address of Block 1 Size of Application Code N1 Byte Count of Block 1 Flag for Block 1 Body of Block 1 Start Address of Block 2 Byte Count of Block 2 4 Bytes 4 Bytes 2 Bytes Byte Count N 2nd Stage Loader 2nd Stage Loader Address Global Header Size of Application Code N1 Application Code Output LDR File 4 Bytes N Bytes 4 Bytes 4 Bytes ...

Page 43: ...trated below ADSP BF535 Processor Memory Ranges Second stage loaders are available for ADSP BF535 processors in Visu alDSP 3 0 and higher They allow booting to L2 memory 0xF000 0000 L1 memory Data Bank A SRAM 0xFF80 0000 Data Bank B SRAM 0xFF90 0000 Instruction SRAM 0xFFA0 0000 Scratchpad SRAM 0xFFB0 0000 SDRAM Bank 0 0x0000 0000 Bank 1 0x0800 0000 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 15 1 La...

Page 44: ...nd 16 bit PROM Flash booting reserve 0xF003 FE00 0xF003 FFFF last 512 bytes For 8 and 16 bit addressable SPI booting reserve 0xF003 FD00 0xF003 FFFF last 768 bytes If segments reside in SDRAM memory configure the SDRAM reg isters accordingly in the second stage loader kernels before booting Modify section of code called SDRAM setup in the second stage loader and rebuild the second stage loader Any...

Page 45: ...n 8 bit external memory is not possible since the minimum width of the External Bus Interface Unit EBIU is 16 bits Load bytes into L1 instruction memory by using the instruction test com mand and data registers as described in the Memory chapter of the appropriate Hardware Reference manual These registers transfer 8 byte sections of data from external memory to internal L1 instruction memory ...

Page 46: ...cription of each boot mode is as follows ADSP BF531 BF532 BF533 Processor On Chip Boot ROM on page 2 17 ADSP BF531 BF532 BF533 Processor Boot Streams on page 2 19 Table 2 2 ADSP BF531 BF532 BF533 Processor Boot Mode Selections Boot Source BMODE 1 0 Execution Start Address ADSP BF531 ADSP BF532 Processors ADSP BF533 Processor Execute from 16 bit External ASYNC Bank0 memory no boot mode or bypass on...

Page 47: ...s set the on chip boot ROM bypasses the full boot sequence and jumps to the start of L1 memory 3 Eventually if bit 4 of the SYSCR register is not set the on chip boot ROM performs the full boot sequence Figure 2 9 Figure 2 8 ADSP BF533 Processors System Reset Configuration Register 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BMODE 1 0 Boot Mode RO 00 Bypass boot ROM execute from 16 bit exter...

Page 48: ...application code DXE into the loadable file by parsing the code and creating a file that consists of different blocks Each block is encapsulated within a 10 byte header which is illustrated in Figure 2 9 and detailed in the following section These headers in turn are read and parsed by the on chip boot ROM during booting The 10 byte header provides all the information the on chip boot ROM requires...

Page 49: ...employ a kernel their boot streams do not include the kernel code and the associated 4 byte header on the top of the kernel code There is also no 4 byte global header Blocks and Block Headers As the loader converts the code from an input DXE file into blocks com prising the output loader file each block is getting preceded by a 10 byte header Figure 2 10 followed by a block body if it is a non zer...

Page 50: ...er for Block 1 Block 1 Header for Block 2 Block 2 Header for DXE2 Count DXE2 Byte Count 4 Byte Address 4 Byte C ount 2 Byte Flag 10 Byte H eader B lock See F lag Inform ation 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Last Block 1 last block 0 not last block Ignore Block 1 ignore block 0 do not ignore block Initialization Block 1 init block 0 non init block Processor Type 1 ADSP BF533 0 ADSP BF531 BF53...

Page 51: ...ck and move on to the next one Currently is not implemented for application code Initialization Block Indicates that the block is to be executed before booting The initialization block indicator allows the on chip boot ROM to execute a number of instruc tions before booting the actual application code When the on chip boot ROM detects an Init Block it boots the block into internal memory and makes...

Page 52: ...k Execution Figure 2 12 ADSP BF531 BF532 BF533 Booting Application Code ADSP BF531 BF532 BF533 Processor Header for Init Block App Code Data Init Block PROM Flash or SPI Device A L1 Memory Init Block SDRAM 0xEF00 0000 On Chip Boot ROM 1eader for L1 Block L1 Block Header for SDRAM Block SDRAM Block Block n 10 Byte Header for Block n ...

Page 53: ...Ms may require different initialization procedure or values 3 A Post Init Section this section restores all the register from the stack Customers should not modify the Pre Init and Post Init Sections The Init Code Section can be modified for a particular application include defBF532 h SECTION program Pre Init Section SP ASTAT Stack Pointer SP is set to the end of SP RETS scratchpad memory 0xFFB00F...

Page 54: ...AM Memory Bank Control Register P0 H EBIU_SDBCTL 16 0xFFFF R0 0x0001 Z W P0 R0 SSYNC P0 L EBIU_SDGCTL 0xFFFF SDRAM Memory Global Control Register P0 H EBIU_SDGCTL 16 0xFFFF R0 L 0x998D R0 H 0x0091 P0 R0 SSYNC Post Init Section L3 SP L2 SP L1 SP L0 SP M3 SP M2 SP M1 SP M0 SP B3 SP B2 SP B1 SP B0 SP I3 SP I2 SP I1 SP I0 SP p5 0 SP r7 0 SP RETS SP ASTAT SP RTS ...

Page 55: ...FF80 7FFF Instruction SRAM 0xFFA0 8000 FFA0 BFFF ADSP BF532 processor Data Bank A SRAM 0xFF80 4000 0xFF80 7FFF Data Bank B SRAM 0xFF90 4000 0xFF90 7FFF Instruction SRAM 0xFFA0 8000 FFA1 3FFF ADSP BF533 processor Data Bank A SRAM 0xFF80 0000 0xFF80 7FFF Data Bank B SRAM 0xFF90 000 0xFF90 7FFF Instruction SRAM 0xFFA0 0000 FFA1 3FFF SDRAM memory Bank 0 0x0000 0000 0x07FF FFFF Booting to scratchpad me...

Page 56: ...M does the following 1 Sends a READ command 0x03 then does a dummy READ 2 Sends an address byte 0x00 then does a dummy READ 3 Sends another byte 0x00 and verifies if the incoming byte is a zero If the byte is a zero an 8 bit addressable SPI memory device is connected 4 If the incoming byte is not a zero the on chip boot ROM sends another byte 0x00 and verifies if the incoming byte is a zero If the...

Page 57: ...hat maps to PF2 The on chip boot ROM sets the Baud Rate register to 133 which based on a 133 MHz system clock results in a 133 MHz 2 133 500 kHz baud rate Analog Devices recommends the following SPI memory devices 8 bit addressable SPI memory 25LC040 from Microchip http www microchip com download lit pline mem ory spi 21204c pdf 16 bit addressable SPI memory 25CL640 from Microchip http www microch...

Page 58: ...ot ROM loads an application program from an external memory device and starts executing that program by jumping to the start of core A s L1 instruction SRAM at address 0xFFA0 0000 Table 2 5 summarizes the boot modes and execution start addresses for ADSP BF561 processors Just like the ADSP BF531 BF532 BF533 processor the ADSP BF561 boot ROM uses the interrupt vectors to stay in supervisor mode The...

Page 59: ...s it With two cores two DXE files can be loaded at once In the real time environment there is no debugger which allows the boot ROM to load the executables into memory ADSP BF561 Processor Boot Streams The loader converts the DXE into a boot stream file LDR by parsing the executable and creating blocks Each block is encapsulated within a 10 byte header The LDR file is burned into the external memo...

Page 60: ...e header tells the boot ROM where in memory to place each block how many bytes to copy and whether the block needs any special processing The header structure is the same as that of the ADSP BF531 BF532 BF533 processors described in Blocks and Block Headers on page 2 19 Each header contains a 4 byte start address for the data block a 4 byte count for the data block and a 2 byte flag word indicatin...

Page 61: ...block header Table 2 7 ADSP BF561 Processor Boot Stream Structure Bit Field Description 0 7 LSB of the Global Header 8 15 8 15 of the Global Header 16 23 16 23 of the Global Header 24 31 MSB of the Global Header 32 39 LSB of the address field of 1st DXE count block no care 40 47 8 15 of the address field of 1st DXE count block no care 48 55 16 23 of the address field of 1st DXE count block no care...

Page 62: ...of the byte count of the 1st data block in 1st DXE 200 207 MSB of the byte count of the 1st data block in 1st DXE 208 215 LSB of the flag word of the 1st block in 1st DXE 216 223 MSB of the flag word of the 1st block in 1st DXE 224 231 Byte 3 of the 1st block of 1st DXE 232 239 Byte 2 of the 1st block of 1st DXE 240 247 Byte 1 of the 1st block of 1st DXE 248 255 Byte 0 of the 1st block of 1st DXE ...

Page 63: ...te count field of the nth block of 1st DXE LSB of the flag word of the nth block of 1st DXE MSB of the flag word of the nth block of 1st DXE Byte 1 of the nth block of 1st DXE Byte 0 of the nth block of 1st DXE LSB of the address field of 2nd DXE count block no care 8 15 of the address field of 2nd DXE count block no care And so on Table 2 7 ADSP BF561 Processor Boot Stream Structure Cont d Bit Fi...

Page 64: ...FF L1 Instruction Cache SRAM 0xFFA1 0000 0xFFA1 3FFF L1 Data Bank A SRAM 0xFF80 0000 0xFF80 3FFF L1 Data Bank A Cache SRAM 0xFF80 4000 0xFF80 7FFF L1 Data Bank B SRAM 0xFF90 0000 0xFF90 3FFF L1 Data Bank B Cache SRAM 0xFF90 4000 0xFF90 7FFF Core B L1 Instruction SRAM 0xFF60 0000 0xFF6 03FFF L1 Instruction Cache SRAM 0xFF61 0000 0xFF61 3FFF L1 Data Bank A SRAM 0xFF40 0000 0xFF40 3FFF L1 Data Bank A...

Page 65: ...ation block must save and restore registers and return to the boot ROM so the boot ROM can load the rest of the blocks For more details see Flags of Block Header on page 2 20 Both the initialization block and second stage loader can be used to force the boot ROM to load a specific DXE from the external memory device if the boot ROM stores multiple executable files The initialization block can mani...

Page 66: ...a separate DXE file for each core The loader combines the contents of the shared memory files sml2 sm sml3 sm into the DXE file for core A p0 dxe The boot ROM only loads one single executable before the ROM jumps to the start of core A instruction SRAM 0xFFA0 0000 When two DXEs must be loaded a second stage loader should be used The second stage boot loader must start at 0xFFA0 0000 The boot ROM l...

Page 67: ...ternal memory Each executable file is pre ceded by a 4 byte count header which is the number of bytes within the executable including headers This information can be used to boot a spe cific DXE into the processor The 4 byte DXE count block is encapsulated within a 10 byte header to be compatible with the silicon revision 0 0 For more information see Blocks and Block Headers on page 2 19 Booting m...

Page 68: ...tion block code change the value of R0 or R3 to point to the external memory location at which the specific application code starts After the processor returns from the initialization block code to the on chip boot ROM the on chip boot ROM continues to boot in bytes from the location specified in the R0 or R3 register Figure 2 13 ADSP BF531 BF32 BF33 BF561 Multi Application Booting 10 Byte Header ...

Page 69: ...2 SP I3 SP B0 SP B1 SP B2 SP B3 SP M0 SP M1 SP M2 SP M3 SP L0 SP L1 SP L2 SP L3 Init Code Section R0 H High Address of DXE Location R0 for Flash Prom Boot R3 for SPI boot R0 L Low Address of DXE Location R0 for Flash Prom Boot R3 for SPI boot Post Init Section L3 SP L2 SP L1 SP L0 SP M3 SP M2 SP M1 SP M0 SP B3 SP B2 SP B1 SP B0 SP I3 SP I2 SP I1 SP I0 SP p5 0 SP MAKE SURE NOT TO RESTORE R0 for Fla...

Page 70: ...nd is the same for all Blackfin processors When you open the Load page the default loader settings for the selected processor are already set Option settings on the Load page correspond to switches displayed on the command line These sections describe how to produce a bootable or non bootable loader file LDR Using Loader Command Line on page 2 40 Using Base Loader on page 2 47 Using Second Stage L...

Page 71: ...rocessor part number for every input DXE if designing multipro cessor systems If the processor is not specified the default is ADSP BF535 switch One or more optional switches to process Switches select operations and modes for the loader Command line switches may be placed on the command line in any order except the order of input files for a multiinput system For a multiinput system the loader pr...

Page 72: ...pts a baud rate for SPI booting only Note Currently supported only for ADSP BF535 processors Valid baud rates and corresponding values are 500K 500 kHz the default 1M 1 MHz 2M 2 MHz Boot kernel loading supports an SPI baud rate up to 2 MHz enc dll_filename Encrypts the data stream from the application DXE files If the file name parameter does not appear on the command line the encryp tion algorith...

Page 73: ...ock and then calls it It is the responsibility of the code within the block to save restore state registers and then perform a RTS back to the ker nel Note This switch cannot be applied to ADSP BF535 processors kb prom kb flash kb spi Specifies the boot mode PROM Flash or SPI for the boot kernel output file if you select to generate two output files from the loader one for the boot kernel and anot...

Page 74: ...ilizes the user specified kernel and ignores the default boot kernel if there is one Note Currently only ADSP BF535 processors have default kernels M Generates make dependencies only no output file will be generated maskaddr Masks all EPROM address bits above or equal to For example maskaddr 29 default masks all the bits above and including A29 ANDed by 0x1FFF FFFF For example 0x2000 0000 becomes ...

Page 75: ...ut file use the kb kf kwidth switches to specify the boot mode the boot format and the boot width for the output kernel file If you intent to use the 02 switch do not combine it with nokernel on ADSP BF535 processors l filename and or init filename on ADSP BF531 BF532 BF535 BF561 processors p Specifies a hex PROM Flash output start address for the application code A valid value is between 0x0 0xFF...

Page 76: ...malous conditions occur Note In the absence of the silicon revision switch the loader selects the greatest silicon revision it is aware of if any Note In the absence of the version parameter a valid version value si revision alone or with an invalid value the loader generates an error v Outputs verbose loader messages and status information as the loader processes files waits Specifies the number ...

Page 77: ... page the default loader settings Loader options for the selected proces sor are already set As an example Figure 2 14 shows the ADSP BF532 processor s default Load settings for PROM booting Command line switches equivalent to the dialog box options are also identified Refer to Command Line Switches on page 2 42 for more information on the switches Figure 2 14 Base Load Page Loader File Options Pa...

Page 78: ...e on chip ROM by setting the no2kernel command line switch as described on page 2 45 For ADSP BF531 BF532 BF533 and ADSP BF561 processors which do not have software boot kernels by default you need to select the boot kernel to use one Boot mode Specifies PROM Flash or SPI as a boot source Boot format Specifies Intel hex ASCII or binary formats Output width Specifies 8 or 16 bits If BMODE 01 or 001...

Page 79: ...cifies a baud rate for SPI booting 500 kHz 1 MHz and 2 MHz The selection is active for ADSP BF535 processors For ADSP BF531 ADSP BF532 and ADSP BF533 processors the field is grayed out Initialization file Directs the loader to include the initialization file Init code The Initialization file selection is active for ADSP BF531 BF532 BF533 and ADSP BF561 pro cessors For ADSP BF535 processors the fie...

Page 80: ...wo output files boot kernel file and appli cation code file select the Output kernel in separate file check box This option boots the second stage loader from one source and the application code from another source If the Output kernel in separate file box is selected you can specify the kernel output file options such as the Boot mode source Boot format and Output width Figure 2 15 ADSP BF53x Pro...

Page 81: ... 6 Specify the Start address FLash PROM output address in hexa decimal format for the kernel code This option allows you to place the kernel file at a specific location within the Flash PROM in the loader file 7 For ADSP BF535 processors only modify the Wait states and Hold time cycles for Flash PROM booting or the Baud rate for SPI booting 8 Click OK to complete the loader setup Using ROM Splitte...

Page 82: ...f the Load page With the Enable ROM splitter box unchecked only TYPE RAM seg ments are processed and all TYPE ROM segments are ignored by the elfloader utility If the box is checked TYPE RAM segments are ignored and TYPE ROM segments are processed by the splitter utility The Mask Address field masks all EPROM address bits above or equal to the number specified For example Mask Address 29 default m...

Page 83: ...000 in the Asynchronous Memory Bank 0 The processor assumes 16 bit memory with valid instructions at that location To create a proper LDR file that can be burned into either a parallel Flash or EPROM device you must modify the standard LDF file in order the reset vector is to be located accordingly The following code fragments illustrate the required modifications in case of an ADSP BF533 processo...

Page 84: ... rom_code MEM_PROGRAM_ROM data_rom INPUT_SECTION_ALIGN 4 INPUT_SECTIONS OBJECTS rom_data MEM_DATA_ROM data_sram INPUT_SECTION_ALIGN 4 INPUT_SECTIONS OBJECTS ram_data MEM_DATA_RAM With the LDF file modified this way the source files can now take advan tage of the newly introduced sections as in Listing 2 5 Listing 2 5 Section Handling Source Files SECTION rom_code _reset_vector l0 0 1 0 l2 0 l3 0 c...

Page 85: ...isualDSP Loader Manual 2 55 for 16 Bit Processors Blackfin Processor Loader Splitter SECTION rom_data VAR myconst x 0xdeadbeef SECTION ram_data VAR myvar y note that y cannot be initialized automatically ...

Page 86: ...Blackfin Processor Loader Guide 2 56 VisualDSP Loader Manual for 16 Bit Processors ...

Page 87: ...195 ADSP 2196 ADSP 21990 ADSP 21991 and ADSP 21992 DSPs The ADSP 2192 12 loader is described in Chapter 4 ADSP 2192 12 DSP Loader on page 4 1 Refer to Introduction on page 1 1 for the loader overview the introduc tory material applies to all processor families Loader operations specific to the listed above processors are detailed in the following sections ADSP 219x DSP Booting on page 3 2 Provides...

Page 88: ...l for more information on system configura tion peripherals registers and operating modes You can run the loader splitter program from a command line or from within the VisualDSP IDDE When working within the VisualDSP specify options via the Load page of the Project Options dialog box Option setting on the Load page correspond to switches displayed on the command line To ensure correct operation o...

Page 89: ...functions as a SPORT or an SPI It is possible for an application to require OPMODE to operate differ ently at runtime than at RESET that is boot from an SPI but use SPORT2 during runtime In this case the boot kernel is responsible for setting OPMODE accordingly at the end of the booting process Therefore software can change OPMODE anytime during runtime as long as the corresponding peripherals are...

Page 90: ...itializing registers among other tasks Ensure that the boot sequence entry code or boot loaded program are not allowed into this space ADSP 219x DSP Boot Streams The ADSP 219x ROM resident loader is designed to parse and load a spe cific boot stream format When booting from an external 8 or 16 bit EPROM the boot stream consists of header and block fields The first header in the boot stream is a co...

Page 91: ...et is the 8 LSBs followed by the next most significant bits 15 8 and so on The third word contains the upper most 8 bits of the 24 bit desti nation address padded suffixed with one byte of zeros The fourth word contains the payload s word count Similar to the address the first octet is the 8 LSBs and the second octet is the 8 MSBs An extra word appears when a checksum function is used to verify bo...

Page 92: ...16 24 When booting from an 8 or 16 bit EPROM direct DSP core accesses and Memory DMA under the control of an EPROM boot routine located in the ROM space are used to load a boot stream formatted program located in the boot space Appropriate packing modes are selected based on the requirements of the boot stream Each page of boot space is 64K words long and 16 bits can address the EPROM per page The...

Page 93: ...follows File2 dxe pd addr switches_specific_to_dxe_file_that_follows File3 dxe File1 dxe is the default application that is booted by the on chip boot kernel after reset Unless the p switch is specified the boot stream of File1 dxe starts at EPROM address 0x000000 If there is a pd addr switch specified for an executable file File dxe the switches between pd and File dxe are called a pd grouping Th...

Page 94: ...m The destination address in the header is same as that of the first loader block in the regular boot stream This means that any data booted by the artificial loader block is to be overwritten by the real data from the regular boot stream The content of this block s payload is the pd value for the next DXE If no pd grouping is specified for the next DXE the pd value for the next DXE is calculated ...

Page 95: ...der proc ADSP 2191 b PROM width 16 app1 dxe app2 dxe pd 0x20000 p 0x20000 width8 o flash ldr app3 dxe pd 0x30000 app4 dxe Since the p value is reset to a zero whenever an o is specified the addresses in the Intel hex record starts at zero for flash ldr 2 Equivalently invoke the loader twice o Output file LDR for the current and following DXEs see o filename on page 3 22 opmode Opmode for the curre...

Page 96: ... Since the default p value is reset to a zero whenever an o is specified the addresses in the Intel hex record has to be explicitly set to 0x20000 for flash ldr It is very likely that second stage loaders and similar type of programs exe cute directly from the EPROM Thus this multiple DXE scenarios are often combined with the features discussed in Enriching Boot EPROMs with No boot Data on page 3 ...

Page 97: ...standard rate anywhere within the UART clocking capabilities Following a hardware or software reset the ADSP 219x DSP monitors the UART transceiver channel and expects the predefined character 0xAA to determine the bit rate The DSP replies an OK string to acknowledge the bit rate Afterwards the host may send the complete boot stream 8 data bits no parity 1 stop bit without further handshake The bo...

Page 98: ...ine in internal ROM space While booting via serial EPROM the highest 16 locations in page 0 program memory block 0x7FF0 to 0x7FFF and the top 272 loca tions of page 0 data memory block 0xFEF0 to 0xFFFF are reserved for use by the ROM boot routine Refer to the Application Note EE 145 for SPI booting examples No booting When BMODE2 0 is strapped to a 000 or 001 the ADSP 219x DSP comes out of hardwar...

Page 99: ... seg_ext_code TYPE PM ROM START 0x010000 END 0x017FFF WIDTH 16 The START END and LENGTH commands expect logical addresses Since the example segment stores 24 bit wide instructions the TYPE PM command defines the logical width of the segment to be 24 bits The example assumes no boot mode 000 and runs from external memory starting at address 0x010000 This is why the WIDTH 16 command sets the physica...

Page 100: ...nd the EPROM is the only device connected to MS0 the first 64K words can be accessed through addresses 0x200000 to 0x20FFFF If a project consists only of two segments seg_ext_data and seg_ext_code a 128K x 16 bit EPROM device would be sufficient to store all the required data and instructions If the loader utility is invoked with the maskaddr 17 switch on page 3 22 all physical address bits greate...

Page 101: ...2x address multiply 02 bytes logical width 01 byte physical width 00000000 reserved 1234 1st data word DM data is 16 bits 5678 9ABC DEF0 4th last data word CRC16 optional controlled by the checksum switch PM Example ext_code TYPE PM ROM START 0x040000 END 0x040007 WIDTH 16 The above PM segment results in the following code 00040000 32 bit logical address field 00000008 32 bit logical length field ...

Page 102: ...inds of LDF segments TYPE RAM segments are passed to the loader s boot stream generator and TYPE ROM segments are passed to its splitter Boot stream and splitter data can be combined within a single EPROM image Assuming a cost sensitive application comprising an ADSP 2196 DSP and a 64 Kbyte EPROM the boot stream probably does not exceed 40 kilobytes 8K x 3 bytes 8K x 2 bytes of length The rest of ...

Page 103: ...x01 3FFF The corresponding LDF file would include the following MEMORY seg_int_code TYPE PM RAM START 0x000000 END 0x000000 WIDTH 24 seg_int_data TYPE DM RAM START 0x008000 END 0x009FFF WIDTH 16 seg_ext_code TYPE PM ROM START 0x012C00 END 0x013FFF WIDTH 8 seg_ext_data TYPE DM ROM START 0x015000 END 0x0157FF WIDTH 8 By default the elfloader emits true EPROM addresses by multiplying the logical addr...

Page 104: ...umes the boot device is connected to the DSP s BMS strobe During runtime typically the MSx strobes are used To use one EPROM for both booting and run time issues set the proper BMS control bits in the E_STAT register If several devices are connected to the individual MSx strobes an off chip AND gate is recommended to OR the BMS and the MS0 strobes properly Please refer to the Application Note EE 1...

Page 105: ...line elfloader sourcefile outputfile proc processor switch where sourcefile Identifies the executable file DXE to be processed into a single processor boot loadable file A file name can include the drive and directory Enclose long file names within straight quotes long file name outputfile Optional name of the loader s output a file with the LDR extension Each run generates a single output file pr...

Page 106: ...d file types File searches are important in the loader operation The loader supports relative and absolute directory names default directories File searches occur as described on page 1 9 File Extensions Table 3 5 lists and describes file types input and output by the loader Table 3 5 File Extensions for ADSP 218x Loader Operation File Extension Description DXE Executable files and boot kernel fil...

Page 107: ... Specifies the base clock divide factor Valid values are 0 to 7 inclusive The default is 5 Note Applies to EPROM and Host boot modes only f hex f ASCII f binary Specifies the boot file s format Valid selections are hex Intel hex 32 ASCII and binary The hexa decimal format is the default For PROM booting Intel hex is the only valid entry When f ASCII and romsplitter are selected regardless of the b...

Page 108: ... relative byte address that is the value in the address portion of the Intel hex information is set to zero The value of zero is the default value but also can be set by PEqualZero The value can be set to the value provided to the pd switch specified by the PEqualPD switch Further it also can be set by specifying a p argument within the pd grouping See ADSP 219x DSP Multiple DXE Support on page 3 ...

Page 109: ...essor for which the loader file is created For example proc ADSP 2191 or proc ADSP 21990 Note proc ADSP 21xx is the preferred form dADSP 21xx is for leg acy support only readall Creates a non bootable image and non boot stream image in the same output file together with the boot loadable image Boot mode must be set to PROM b PROM and format must be set to hex f hex romsplitter Creates a non bootab...

Page 110: ... Specifies the bus width in bits for EPROM Flash or Host booting Valid numbers are 8 default and 16 Width must correspond to the EMICTL register s E_BWS bit For multi DXE processing if the width changes from one pd group to the next a new LDR file must be created by specifying o in the pd group where width has changed See o filename and pd address inputfile for details Table 3 6 Loader Command Lin...

Page 111: ...g is not supported for an ADSP 2192 12 DSP Refer to Introduction on page 1 1 for the loader overview the introduc tory material applies to all processor families Loader operations specific to ADSP 2192 12 DSPs ADSP 2192 for short are detailed in the follow ing sections ADSP 2192 DSP Booting on page 4 2 Provides general information on the loader commands and operations ADSP 2192 DSP Loader Guide on...

Page 112: ...erence RTBL that can be used to boot load an ADSP 2192 12 EZ KIT Lite evaluation system on Windows 98 and Windows 2000 platforms You can run the loader from a command line or directly from within the VisualDSP IDDE When working from the VisualDSP specify the loader options via the Load page of the Project Options dialog box Option setting on the Load page correspond to switches displayed on the co...

Page 113: ... USB and software reset The reset type is specified by bits 8 and 9 CRST 1 0 of the Chip Mode Status Register CMSR as follows in Table 4 1 If the reset source is a power on reset the processors s BUSMODE pins are read to determine whether boot is via PCI USB Sub ISA or CardBUS interface Table 4 2 Table 4 1 ADSP 2192 12 DSP CMSR Settings CMSR Setting RESET Type CRST 1 0 00 Power on reset CRST 1 0 1...

Page 114: ...ng control to PCI or USB is to enter an infinite loop waiting for instructions A predefined memory address DM 0x000000 is regularly checked for commands Once the PCI or USB device has completed boot ing the DSP they can write an instruction to this predefined location and have the DSP execute any of supported commands Refer to the datasheet ADSP 219x 2192 DSP Hardware Reference and Application Not...

Page 115: ...ly you create the EXE file see Creating a EXE File on page 4 6 The following procedure suggests one method to build the DXE file using the VisualDSP environment You may choose to combine steps or use the loader s command line instead To build the DXE files from VisualDSP 1 Open the Project page of the Project Options dialog box 2 Under Processor select ADSP 2192 12 Figure 4 1 ADSP 2192 12 DSP Load...

Page 116: ...rocessors or online Help If a DSP executable file changes rerun the loader The rerun creates a new H file from the DXE OVL and SM input files Then run the RTBL as described in Creating a EXE File on page 4 6 to build an EXE file from the H file Automate these tasks from the VisualDSP environment by specifying the target type as DSP Loader file on the Project page of the Project Options dialog box ...

Page 117: ...nnot access the PCI mapped memory of the ADSP 2192 DSP directly A driver is mandatory Reference RTBL Creating the RTBL and driver can be a complex task especially the first time To facilitate the process VisualDSP includes a reference RTBL in the form of a Microsoft VisualC 6 0 project named reference_rtbl dsp This project is located in the ldr subdirectory of your VisualDSP installation directory...

Page 118: ...aded to the DSP to insert the correct addresses at runtime The DSP cannot access the Windows virtual memory space An overlay must be copied from virtual memory space to PCI memory space which can only be allocated in limited quantities by the PCI driver However the loader output considers the need for run time patches of the executable A portion of the data structure created by the loader is for t...

Page 119: ... exact the overlay live address of each overlay according to the provided offset value Instead of defining OvlPciAdrTbl define OvlMgrTbl in the assembly source code This symbol should contain the start address of the overlay table and the overlay table can be declared and defined in your assembly source code The loader gets this symbol s value and makes the define statement along with the other de...

Page 120: ...wing syntax for the loader s command line when there is only one input executable DXE elfloader core0 sourcefile o outputfile proc ADSP 2192 switch or elfloader core1 sourcefile o outputfile proc ADSP 2192 switch where core0 core1 Specify that the sourcefile is for core0 or core1 respectively The loader makes up the array and structure names according to the supplied core number sourcefile Identif...

Page 121: ...efile0 as the input file to process for core 0 The loader creates the array and structure names according to the supplied core number Before running the loader ensure that all OVL and SM files reside in the same working directory as the executables The loader automatically opens the overlay and shared memory files to read in the data while process ing the executables core1 sourcefile1 Identifies t...

Page 122: ...e name as an optional parameter Table 4 4 on page 4 13 lists types the loader expect on files File searches are impor tant in the loader operation The loader supports relative and absolute directory names default directories File searches occur as follows Specified path If you include relative or absolute path informa tion in a file name the loader searches only in that location for the file Defau...

Page 123: ...hared memory files but does not expect these files on the command line Place SM files in the same directory as the DXE file that refers to them the loader can locate them when processing the DXE file H Loader output files C language header files Table 4 4 ADSP 2192 DSP Loader Command Line Switches Switch Description f format Specifies the boot file format Prepares an output file in the specified f...

Page 124: ...of two forms One or more decimal digits followed by a point followed by one or two decimal digits Examples of revisions are 0 0 1 12 23 1 Version 0 1 is distinct from and lower than version 0 10 The digits to the left of the point specify the chip tapeout number the digits to the right of the point identify the metal mask revision number The number to the right of the point can not exceed decimal ...

Page 125: ... the following sections ADSP 218x DSP Loader Guide on page 5 1 Explains how a boot loadable file is created written to and run from an ADSP 218x DSP s internal memory ADSP 218x DSP Splitter Guide on page 5 15 Explains how a non bootable PROM image file is created and exe cuted from an ADSP 218x DSP s external memory ADSP 218x DSP Loader Guide The loader splitter elfspl21 exe processes an executabl...

Page 126: ...boot loadable file you can specify the loader options from within the VisualDSP environment VisualDSP invokes the elfspl21 and builds the output file To generate a non bootable PROM file you must run the elfspl21 utility from a command line To ensure correct operation of the loader familiarize yourself with Boot Modes on page 5 2 Determining Boot Modes on page 5 4 EPROM Booting BDMA on page 5 6 Ho...

Page 127: ...mode Host Booting IDMA Mode In this mode the DSP does not start program execution immediately but waits passively until a host DSP such as a microcontroller or another ADSP 218x part writes project data into the DSP s on chip memory through the IDMA interface The elfspl21 loader processes the project data but the data may require post processing because each type of host processor requires its ind...

Page 128: ... until all 32 words have been loaded 0 1 IDMA is used to load any internal memory as desired Program execution is held off until internal program memory location 0 is written to 1 X Bootstrap is disabled Program execution immediately starts from location 0 Table 5 2 Boot Modes ADSP 2184 to ADSP 2189 DSPs Mode D Mode C Mode B Mode A Description X 0 0 0 BDMA is used to load the first 32 program memo...

Page 129: ...d the first 32 program memory words from byte memory space Program execution is held off until all 32 words have been loaded Chip is configured in Host mode IACK requires external pull down Note Requires additional hardware 1 1 0 1 IDMA is used to load any internal memory as desired Program execution is held off until the host writes to internal program memory location 0 The chip is con figured in...

Page 130: ...g continues and the preloader loads a set of so called page loaders beginning at PM address 0x0020 After the preloader terminates the DSP executes the page loaders which load the project data page by page The loader uses a default preloader You can force the loader with the uload switch to use a customized preloader to reduce wait states or to implement a boot management scenario discussed in deta...

Page 131: ... internal PM memory and issues a context reset once it has finished The program counter resets to 0x0000 and pro gram execution begins Refer to the ADSP 218x DSP Hardware Reference for a detailed descrip tion of BDMA capabilities You can debug the EPROM booting process using the VisualDSP simulator by loading the BNM file Settings Sim ulator and then resetting Debug Reset the DSP to start booting ...

Page 132: ...18 x 1 Specifies the target processor Always specify either 2181 or 218x when working with an ADSP 218x DSP see Table 5 5 on page 5 10 The sourcefile and outputfile names must be placed first on the command line Command line switches may occur in any order except for the 2181 or 218x and loader switches When required the 2181 or 218x and loader switches follow the outputfile name the 2181 or 218x ...

Page 133: ... directory names default directories File searches occur as described on page 1 9 File Extensions Table 5 4 lists and describes file types input and output by the loader Loader Switches Table 5 5 lists and describes the loader switches used in BDMA mode Table 5 4 ADSP 218x Loader File Extensions File Extension Description DXE Executable files and boot kernel files OVL Overlay memory files The load...

Page 134: ...the ADSP 218x default loader noloader Excludes the ADSP 218x loader When used with 2181 loader or 218x loader generates a byte memory image without a loader This suppresses the preloader and page loaders bdma inputfile start_address Use with 2181 loader Specifies placement of an additional DXE file inputfile in byte memory starting at the specified address The loader returns an error if the specif...

Page 135: ... the IDMA port The DSP auto increments its address counter Figure 5 1 on page 5 12 illustrates the algorithm the host processor must compute to boot the DSP successfully uload filename Reads the BDMA preloader from filename doj The preloader must consist of exactly 32 instructions Preloaders gener ated by the elfspl21 utility automatically determine the BWCOUNT value which mirrors the numbers of i...

Page 136: ... files in IDM format It is up to the user to post process this file in a customized way Due to hardware restrictions IDMA booting of off chip memories is not possible Refer to the description of IDMA capabilities in the ADSP 218x DSP Hardware Reference Figure 5 1 Host Processor Algorithm Read next word count N Read IDMA Control value and perform Address Latch Cycle N 0xFFFF YES NO N 0x0000 YES NO ...

Page 137: ...developers working with ADSP 218x DSPs use the loader instead of the splitter For ADSP 218x DSPs splitter and loader features are handled by Table 5 6 ADSP 218x DSP IDMA Command Line Switches Switch Description sourcefile Specifies the executable file DXE to be processed for a single processor boot loadable file outputfile Specifies the output file IDM 218 x 1 Specifies the target processor 2181 A...

Page 138: ...5 14 VisualDSP 3 5 Loader Manual for 16 Bit Processors the elfspl21 exe The splitter must be invoked by a completely different set of command line switches Refer to the following ADSP 218x DSP Splitter Guide for more information ...

Page 139: ...ter command line switches Using Splitter You must run the splitter PROM splitter from a command line You cannot generate a non bootable PROM file from within the VisualDSP environment To automate the process specify the splitter command line within VisualDSP from the Post Build page of the Project Options dialog box The ADSP 218x splitter generates images for external PMOVLAY 1 and 2 and DMOVLAY 1...

Page 140: ... DXE to be processed for a non bootable PROM image file A file name can include the drive and directory Enclose long file names within straight quotes long file name outputfile Optional name of the splitter s output a PROM file with the BNL BNU or BNM file extension switch One or more optional switches to process Switches select operations and modes for the splitter pm dm Indicates that either pm ...

Page 141: ...t file extension Use dif ferent names so the output of the second run does not overwrite the output of the first run The output names are pm_stuff s_ and dm_stuff s_ my_proj dxe Specify an executable file to process into a non bootable PROM image file File Searches Many splitter switches take a file name as an optional parameter Table 5 7 lists the type of files names and extensions that the split...

Page 142: ... specified the name of the sourcefile executable file is used for the output The extension depends on the output format byte Produces byte stream output format dm Extracts data memory Extracts segments from the executable declared as data memory The splitter generates two one byte files BNM contains the upper bytes of the 16 bit data words BNL contains the lower bytes i Produces Intel hex output f...

Page 143: ...litter s Produces Motorola S1 output format us us2 ui Produces a byte stacked format file for 8 bit memory us yields Motorola S1 output format us2 yields Motorola S2 output format ui yields Intel hex output format Table 5 8 Splitter Command Line Switches Cont d Switch Description ...

Page 144: ...ADSP 218x DSP Splitter Guide 5 20 VisualDSP 3 5 Loader Manual for 16 Bit Processors ...

Page 145: ...development tool This appendix describes file formats that are prepared as inputs and produced as outputs The appendix describes three types of files Source Files on page A 2 Build Files on page A 5 Debugger Files on page A 9 Most of the development tools use industry standard file formats These formats are described in Format References on page A 10 ...

Page 146: ...er directives possibly a mixture of assembly code and direc tives and typically preprocessor commands Several dialects of C code are supported pure portable ANSI C and at least two subtypes1 of ANSI C with ADI extensions These extensions include memory type designations for certain data objects and segment directives used by the linker to structure and place executable files The C C compiler run t...

Page 147: ...ata These files provide initialization data for an assembler VAR directive or serve in other tool operations When a VAR directive uses a DAT file for data initialization the assembler reads the data file and initializes the buffer in the output object file DOJ Data files have one data value per line and may have any number of lines The DAT extension is explanatory or mnemonic A directive to includ...

Page 148: ... information on macros and other preprocessor commands see the Visu alDSP 3 5 Assembler and Preprocessor Manual for 16 Bit Processors Linker Description Files Linker Description Files LDF are ASCII text files that contain commands for the linker in the linker s scripting language For information on this scripting language see the VisualDSP 3 5 Linker and Utilities Manual for 16 Bit Processors Tabl...

Page 149: ...escribes the following build file formats Assembler Object Files on page A 5 Library Files on page A 6 Linker Output Files on page A 6 Memory Map Files on page A 7 Loader Output Files in Intel Hex 32 Format on page A 7 Splitter Output Files in ASCII Format on page A 9 Assembler Object Files Assembler output object files DOJ are binary executable and linkable files ELF Object files contain relocata...

Page 150: ...de and debugging information The linker fully resolves addresses in executable files For information on the ELF format used for executable files see the TIS Com mittee texts cited in Format References on page A 10 The loaders splitters are used to convert executable files into boot load able or non bootable files Executable files are converted into a boot loadable file LDR for the ADI processors u...

Page 151: ... for the whole series of memory chips to be programmed The following example shows how the Intel hex 32 format appears in the loader s output file Each line in the Intel hex 32 file contains an extended linear address record a data record or the end of file record 020000040000FA Extended linear address record 0402100000FE03F0F9 Data record 00000001FF End of file record Extended linear address reco...

Page 152: ...ys 0000 04 Record type 0000 Offset address FA Checksum Table A 3 Data Record Example Field Purpose 0402100000FE03F0F9 Example record Start character 04 Byte count of this record 0210 Address 00 Record type 00 First data byte F0 Last data byte F9 Checksum Table A 4 End of File Record Example Field Purpose 00000001FF End of file record Start character 00 Byte count zero for this record 0000 Address ...

Page 153: ...e file types produced by the linker DXE SM OVL To simulate I O the debugger also supports the assembler s data file format DAT and the loader s loadable file formats LDR The standard hexadecimal format for a SPORT data file is one integer value per line Hexadecimal numbers do not require an 0x prefix A value can have any number of digits but is read into the SPORT register as follows The hexadecim...

Page 154: ...le and Linkable Format ELF V1 1 from the Portable Formats Specification V1 1 Tools Interface Standards TIS Committee Go to http developer intel com vtune tis htm 1993 Debugging Information Format DWARF V1 1 from the Portable Formats Specification V1 1 UNIX International Inc Go to http developer intel com vtune tis htm Table A 5 SPORT Data File Example Hex Number Binary Number Truncated Filled A5A5...

Page 155: ...t files A 4 LDR files 2 8 2 42 5 1 ASCII format A 9 hex format A 7 splitter output A 9 MAP memory map files A 7 OVL overlay memory files 5 9 A 6 SM shared memory files 4 10 4 11 A 6 TXT ASCII text files A 5 Numerics 16 bit addressable SPI memory 2 27 2184 5 6 8 9 loader switch 5 10 5 13 218x 1 loader switch 5 10 5 13 24 bit addressable SPI memory 2 27 8 bit addressable SPI memory 2 27 A ADSP 218x ...

Page 156: ... programs 3 19 ADSP 2192 Boot Loader switches dADSP2192 4 14 ADSP 2192 loader switches help 4 13 ADSP 2192 12 DSPs boot loader utility 4 10 CMSR settings 4 3 loader 4 2 4 4 ADSP 2192 12 loader switches f format 4 13 M 4 13 MM 4 13 Mo filename 4 14 Mt filename 4 14 o filename 4 14 proc ADSP 2192 4 14 verbose 4 14 ADSP 219x DSPs boot streams 3 4 elfloader exe 3 2 ADSP 219x loader switches b type 3 2...

Page 157: ... 8 2 45 2 48 archive files A 6 see library files A 6 assembler source files ASM A 3 assembling 1 2 assembly initialization data files DAT A 3 asynchronous memory bank 0 2 53 B b boot mode loader switch 2 42 3 21 baud rate 2 49 baudrate loader switch 2 42 BDMA interface 5 3 5 4 transfers 5 7 bdma input start address loader switch 5 10 bdmaload loader switch 5 10 Blackfin loader default settings 2 4...

Page 158: ...ng 2 26 start addresses 2 16 SYSCR register 2 29 block flags 2 13 headers 2 13 2 18 2 30 2 35 3 5 structure 2 19 blocksize loader switch 3 21 BMODE pin settings 2 2 ADSP 2181 DSPs 5 4 ADSP 2183 DSPs 5 4 ADSP 2184 5 6 7 8 9 DSPs 5 4 ADSP 219x DSPs 3 3 ADSP BF531 32 33 processors 2 16 ADSP BF535 processors 2 3 boot file format specifying 2 42 3 21 boot kernel 1 7 omitting in output 2 45 setting for ...

Page 159: ... processors 2 28 EPROM BDMA 5 3 5 6 host 3 10 host IDMA 5 3 no boot mode 2 3 2 16 3 12 5 3 5 15 parallel EPROM 3 4 ROM bypass 2 4 see also SPI booting serial EPROM 3 12 UART part 3 11 via UART on ADSP 219x 3 11 without boot kernel 2 45 boot loadable files 1 4 5 1 bootstraps 2 45 5 4 5 6 build files description of A 5 loader options 4 6 BUSMODE pin settings 4 3 bypassing boot 2 29 byte loader switc...

Page 160: ...er 3 18 EEPROM memory 2 28 2 29 ELF file dumper references A 10 EMICTL register 3 24 emulator 1 2 enc dll_filename loader switch 2 42 EPROM 5 7 output 2 8 2 42 with no boot data 3 16 excluding ADSP 218x loader 5 10 Executable and Linkable Format ELF 1 2 executable files 1 4 A 6 External Bus Interface Unit EBIU 2 15 external memory 1 4 2 5 2 6 2 15 2 37 EZ KIT Lite boards 1 3 F f file format loader...

Page 161: ...de ADSP 218x DSPs 5 4 G ghc loader switch 2 43 global headers 2 11 2 12 2 30 3 4 H headers 2 37 block headers 2 13 help loader switch 2 43 3 21 4 13 5 10 hex format files LDR A 7 HoldTime loader switch 2 43 host booting ADSP 218x DSPs 5 5 5 11 host booting mode overview 1 6 host processors 1 4 5 3 5 11 host3bytes loader switch 3 21 I i hex splitter switch 5 18 IDMA 5 11 control register 5 11 creat...

Page 162: ... 1 2 loader ADSP 218x DSPs 1 4 3 1 5 1 5 2 ADSP 2191 processors 3 19 ADSP 2192 12 DSP 4 1 ADSP 219x DSPs 3 2 boot kernel 1 7 3 4 build options 4 6 for ADSP 218x processors 5 1 hex format files A 7 settings selection 3 21 4 13 5 9 loader loader switch 5 10 M M loader switch 2 44 3 21 4 13 maskaddr loader switch 2 44 3 22 masking EPROM address bits 2 44 MaxBlockSize loader switch 2 44 memory ranges ...

Page 163: ...rTbl symbol 4 9 OvlPciAdrTbl symbol 4 9 P p loader switch 2 45 3 22 page loaders 5 6 5 10 PCI drivers run time boot loader 4 8 pd loader switch 3 23 pdAddrNext loader switch 3 23 pEqualPd loader switch 3 22 pEqualZero loader switch 3 22 pm memory 5 7 5 11 pm splitter switch 5 18 PMOVLAY memory page 5 15 power ups 1 5 preloader 5 10 preloaders ADSP 218x DSPs 5 6 proc loader switch 2 45 3 23 4 14 pr...

Page 164: ...ings 2 49 restrictions 2 14 selecting 2 48 setting options 2 49 shared memory 2 36 silicon revision setting 2 46 4 14 simulating booting process 5 7 simulator 1 2 1 3 si revision loader switch 4 14 si revision loader switch 2 46 slave processors 1 4 5 11 software resets 1 5 source files 1 2 assembly instructions A 3 C C A 2 fixed point data A 3 specifying format byte stream 5 10 Intel hex 5 10 Mot...

Page 165: ...loader switch 5 11 us splitter switch 5 19 user interrupts 2 28 utilities elfloader exe ADSP 219x 3 1 V v verbose loader switch 2 46 3 23 4 14 VisualDSP Load page 5 2 5 6 Load page Boot kernel options 2 49 Load page ROM splitter options 2 52 W wait states 2 46 2 48 5 6 waits loader switch 2 46 3 24 width loader switch 2 46 3 5 3 24 Windows drivers ADSP 2192 12 loader 4 7 Z zero fill blocks 2 21 ...

Page 166: ...INDEX I 12 VisualDSP Loader Manual for 16 Bit Processors ...

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Analog Devices VISUALDSP++ 3.5, Manual

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