Analog Devices VISUALDSP++ 3.5, Manual

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Blackfin Processor Booting
2-34 Vi+ Loader Manual
for 16-Bit Processors
ADSP-BF561 Processor Memory Ranges
The on-chip boot ROM of the ADSP-BF561 processor can load a full
application to the various memories of both cores. Booting is allowed to
the following memory ranges. The boot ROM clears these memory ranges
before booting in a new application.
• Core A
"
L1 Instruction SRAM (
0xFFA0 0000
–
0xFFA0 3FFF
)
"
L1 Instruction Cache/SRAM (
0xFFA1 0000
–
0xFFA1 3FFF
)
"
L1 Data Bank A SRAM (
0xFF80 0000
–
0xFF80 3FFF
)
"
L1 Data Bank A Cache/SRAM (
0xFF80 4000
–
0xFF80 7FFF
)
"
L1 Data Bank B SRAM (
0xFF90 0000
–
0xFF90 3FFF
)
"
L1 Data Bank B Cache/SRAM (
0xFF90 4000
–
0xFF90 7FFF
)
• Core B
"
L1 Instruction SRAM (
0xFF60 0000
–
0xFF6 03FFF
)
"
L1 Instruction Cache/SRAM (
0xFF61 0000
–
0xFF61 3FFF
)
"
L1 Data Bank A SRAM (
0xFF40 0000
–
0xFF40 3FFF
)
"
L1 Data Bank A Cache/SRAM (
0xFF40 4000
–
0xFF40 7FFF
)
"
L1 Data Bank B SRAM (
0xFF50 0000
–
0xFF50 3FFF
)
"
L1 Data Bank B Cache/SRAM (
0xFF50 4000
–
0xFF50 7FFF
)
• Four Banks of Configurable Synchronous DRAM
(
0x0000 0000
–(up to)
0x1FFF FFFF
)