5.2 Electrical Design Power
The following table lists the Thermal Design Current (TDC) numbers for all GPU
power rails. Designers must ensure that their regulator circuits are capable of
supplying continuous TDC safely. The regulator circuits must also meet AMD's
Electrical Design Current (EDC) requirement that is defined as the minimum current
for which the voltage regulator must be capable of safely supplying for a minimum of
1 ms. This means that if a voltage regulator design can safely supply this amount of
current for more than 1 ms, it meets AMD's EDC criterion. EDC can be estimated tobe
1.5 times of TDC unless otherwise specified.
It is required that AMD's SVI2-compliant voltage controllers be used on all "Vega 10"
designs for VDDCR_SOC. A SVI2-compliant voltage controller has two independent
voltage domains built in such that one controller can deliver two power rails to the
GPU (the main domain powers VDDCR_SOC, and the second domain powers
VDDIO_MEM and VDDCR_HBM that are merged on the PCB), saving both cost and
space compared to two-regulator solutions. Both voltage outputs are controlled
through the high-speed SVI2 bus from dedicated GPU pins.
On "Vega 10"", the boot voltage of the SVI2 regulator is fixed at 0.9 V by default for
both domains controlled by the GPU. Overwriting of the SVI2 boot-VID on the PCB is
not allowed. 0.9 V may not be sufficient for HBM to power up properly if the second
domain of the SVI2 regulator powers VDDIO_MEM/VDDCR_HBM rails. Contact AMD
for guidance on setting the second domain voltage to meet HBM power up
requirements.
All voltage regulators that are compliant with AMD's SVI2 specification use the SVT
pin to serially stream real-time voltage and current telemetry to the GPU. "Vega 10"
uses the telemetry information to enable power management features. In order to
maintain the accuracy of the current measurement, it is required that the passive
current-sensing components have a tolerance less than or equal to ±5%. For example,
if an inductor DCR (direct current resistance) is being used as the current-sensing
element, the tolerance of the DCR must be less than or equal to ±5%. Full-scale
current calibration is also required. Please refer to AMD's application note, order#
54265, for details on the calibration procedure.
For the power-up sequence requirements affected by the adoption of SVI2-compliant
voltage regulators, refer to
Power-up/down Sequence (p. 61)
To allow for driver optimizations, faster CPUs, and new applications, designers need
to provide adequate electrical margins.
The numbers are preliminary estimates and subject to change.
Table 5–2 Regulator Guidelines
Rail Name
Nominal
Voltage
DC Tolerance
AC Tolerance
Maximum
Current
Notes
VDDCR_SOC
0.80 V to 1.25
V
VID_VDDC
±1.25% -
I_VDDC × 0.25
mΩ
See Section
Transient
Behavior
300 A (TDC)
760 A (EDC)
1, 2, 4, 9,
10
VDDCR_HBM
VDDIO_MEM
1.35 V
±3%
±3%
20 A (TDC)
35 A (EDC)
3
VDDCI_MEM
0.90 V
±3%
±3%
5 A (TDC)
VDD_080
VDDCR_BACO
VDD_080_EFUSE
0.90 V
±3%
±3%
5 A (TDC)
8
58
Electrical Characteristics
"Vega 10" Databook
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2017
Advanced Micro Devices, Inc.
AMD Confidential - Do not duplicate.
