Table 4–5 Backlight PWM Parameters
Parameter
Description
Min Typ Max Unit
REF
xtal_freq or xtal_freq × 2
—
27
or
54
—
MHz
F
PWM
Backlight PWM signal frequency.
= REF / ( [ (BL_PWM_PERIOD) ×
(BL_PWM_REF_DIV) ] )
where
REF
is the input reference clock frequency (typically 27 or
54 MHz),
BL_PWM_REF_DIV
is a 16-bit value specifying the division
factor for this input reference clock, and
BL_PWM_PERIOD
is a 16-
bit value representing the period of the backlight PWM signal in
units of divided input reference clock cycles.
Typical Range: 55 Hz to 50 kHz.
0.007
—
13 M
Hz
R
DUTY
Active duty cycle ratio.
= (BL_ACTIVE_INT_FRAC_CNT) / (BL_PWM_PERIOD)
Minimum duty cycle increment size is (1/65535) of
BL_PWM_PERIOD.
0
—
100
%
The backlight pulse width modulation circuit generates a backlight PWM signal with
a frequency:
= REFCLK / ( [ (BL_PWM_PERIOD) * (BL_PWM_REF_DIV) ] )
REFCLK
is the input reference clock frequency (typically 27 or 54 MHz).
BL_PWM_REF_DIV
is a 16-bit value specifying the division factor for this input reference
clock.
BL_PWM_PERIOD
is a 16-bit value representing the period of the backlight PWM signal
in units of divided input reference clock cycles.
To set the backlight modulation,
1.
Set the coarse frequency by selecting BL_PWM_REF_DIV:
BL_PWM_REF_DIV = ceil (REF / (65535 ×
FTARGET))
2.
Compute the fine frequency by selecting the period BL_PWM_PERIOD:
BL_PWM_PERIOD = ceil (REF / (FTARGET ×
BL_PWM_REF_DIV))
The period should be a value between 1 and 65535.
3.
Compute the actual frequency:
FINIT = REF / ((BL_PWM_PERIOD) ×
(BL_PWM_REF_DIV))
4.
Compute the relative error:
EINIT = (FTARGET – FINIT) / FTARGET
Note:
•
For 50-kHz FTARGET, EINIT will equal zero (no error).
•
For 55-Hz FTARGET, EINIT will be less than 0.0006%.
•
The number of usable steps for the active duty cycle is (BL_PWM_PERIOD
+ 1), that is from 0% up to 100% active duty cycle.
Timing Specifications
55
©
2017
Advanced Micro Devices, Inc.
AMD Confidential - Do not duplicate.
"Vega 10" Databook
56006_1.00