3.18 PLL Interface
Table 3–19 PLL Interface
Pin Name
Type
Description
XTALIN
I
Connect a 27-MHz parallel-resonant crystal between XTALIN and
XTALOUT as a reference clock to the GPU.
Crystal characteristics:
•
ESR: < 80 Ω.
•
Combined frequency tolerance and stability: ±30 ppm max.
A 1-MΩ resistor must be connected between XTALIN and XTALOUT
when a crystal is used.
Capacitive loading from the package and PCB trace should be
subtracted from the C1 and C2 capacitor values.
XTALOUT
O
See above.
REFCLKN
REFCLKP
I
100 MHz differential reference clock (+/-) input for GPU PLLs,
e.g.,TMDP PLL Display PLL.
200 ps (max) cycle to cycle jitter.
300 ps (max) long term jitter (10,000 cycles after the trigger edge).
Non-spread.
OSC_GAIN[0:2]
I/O
3.3 V
(VDDAN_33)
Provide a pull-up resistor to 3.3 V and a pull-down resistor to GND for
each pin on the PCB.
By default, install only pull-up resistors on OSC_GAIN[2:1], and install
only pull-down resistor on OSC_GAIN[0].
Note: Both the 27-MHz crystal and 100-MHz differential clock must be provided to the GPU.
Table 3–20 External Input Clock Requirements for REFCLKN/P
Symbol Parameter and test conditions
Min
Typ Max Units Notes
Freq
Frequency
100
MHz
V
IH
Differential Input High Voltage
+150
mV
Differential waveform
V
IL
Differential Input Differential
waveform
-150
mV
Differential waveform
V
CROSS
Absolute crossing point voltage
+250
+550 mV
Single-ended crossing
ΔV
CROS
Variation of Vcross over all rising
clock edges
+140 mV
V
swing
Voltage Swing
-0.3
0.76 1
V
Single-Ended including
overshoot/undershoot
T
fall
/T
rise
Rise/Fall time
0.6
4.0
V/ns
Measured from 150-mV to
150-mV differential
Signal Descriptions
35
©
2017
Advanced Micro Devices, Inc.
AMD Confidential - Do not duplicate.
"Vega 10" Databook
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