3.10 AMD SVI2 Master Interface
Table 3–11 AMD SVI2 Master Interface
Pin Name
Type
PD/PU
Description
GPIO_SVC0
I/O
1.8 V
(VDDAN_18)
On-die PU
Serial VID clock.
Push-pull clock output for the SVI2
data bus; driven by the GPU. Point-to-
point connection to the SVI2 voltage
regulator controller.
GPIO_SVD0
I/O
1.8 V
(VDDAN_18)
On-die PD
Serial VID data.
Push-pull data output for the SVI2 data
bus; driven by the GPU. Sets the
voltage, power-state indicator, load-
line slope, and voltage offsets for two
voltage rails. Point-to-point connection
to the SVI2 voltage regulator
controller.
GPIO_SVT0
I/O
1.8 V
(VDDAN_18)
-
Serial VID telemetry.
Push-pull data input driven by the SVI2
voltage regulator controller.
Continuously streams the voltage and
current telemetry information to the
GPU. Also provides an indication when
positive voltage transitions are
complete (VOTFC).
Note: On "Vega 10", the boot voltage of the SVI2 regulator is 0.9 V controlled by the GPU;
overwriting of boot-VID on the PCB is not allowed. If the second domain of the SVI2 regulator
is used to power a GPU rail (e.g., VDDCR_HBM/VDDIO_MEM) that cannot work with 0.9 V,
contact AMD for alternative solutions.
3.11 Panel Control Interface
Note: All signals in this interface can be unconnected if not used. This interface may
be used for eDP panels.
Table 3–12 Panel Control Interface
Pin Name
Type
PD/PU
Description
DIGON
O
3.3 V
(VDDAN_33)
PD
Controls panel digital power on/off.
Note: External pull-down resistor is recommended.
BL_PWM_DIM
O
3.3 V
(VDDAN_33)
PD
LCD PWM (Pulse Width Modulated) output for adjustment of
LCD brightness.
Active high.
BL_PWM_DIM can be used to control backlight on/off (backlight
enable) by setting BL_PWM_CNTL.BL_PWM_EN = 0.
Note: External pull-down resistor is recommended.
BL_ENABLE
I/O
3.3 V
(VDDAN_33)
PD-
reset
Controls backlight on/off.
Active high.
Note: External pull-down resistor is recommended.
Signal Descriptions
29
©
2017
Advanced Micro Devices, Inc.
AMD Confidential - Do not duplicate.
"Vega 10" Databook
56006_1.00
