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Ball Reference

Signal Name

N39

DFTIO_300

N40

DFTIO_287

N41

VSS

N42

DFTIO_260

N43

DFTIO_250

N44

DFTIO_251

N45

VDDCR_SOC

P1

VSS

P2

TX5P_DPE0P

P3

TX5M_DPE0N

P4

VSS

P5

AUX_ZVSS

P6

GENERICD_HPD3

P7

VSS

P8

RSVD

P9

DFTIO_15

P10

RSVD

P11

VSS

P12

VSS

P13

VDDCR_SOC

P14

VDDCR_SOC

P15

VSS

P16

VSS

P17

VDDCR_SOC

P18

VDDCR_SOC

P19

VSS

P20

VSS

P21

VDDCR_SOC

P22

VDDCR_SOC

P23

VSS

P24

VSS

P25

VDDCR_SOC

P26

VDDCR_SOC

P27

VSS

P28

VSS

P29

VDDCR_SOC

P30

VDDCR_SOC

P31

VSS

P32

VSS

P33

VSS

P34

VSS

P35

VSS

Pin Listings

93

©

2017

Advanced Micro Devices, Inc.

AMD Confidential - Do not duplicate.

"Vega 10" Databook

56006_1.00

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Summary of Contents for Vega 10

Page 1: ...Vega 10 Databook Technical Reference Manual AMD Confidential Part Number 56006_1 00...

Page 2: ...Khronos Dolby is a registered trademark of Dolby Laboratories HDMI the HDMI logo and High Definition Multimedia Interface are licensed trademarks of HDMI Licensing LLC DirectX Microsoft and Windows ar...

Page 3: ...1 xx are documents with substantial info Revision numbers 2 xx are documents with complete information Full Release Revision numbers 3 xx are for production Revision History Rev 1 00 May 17 2017 Prel...

Page 4: ...iv Revision History Vega 10 Databook 56006_1 00 2017 Advanced Micro Devices Inc AMD Confidential Do not duplicate...

Page 5: ...4 Video Acceleration Features 13 2 5 Video Codec Engine VCE Features 14 2 6 PCI Express Bus Support Features 15 2 7 Power Management Features 15 2 8 Spread spectrum Support 16 2 8 1 Engine Spread spe...

Page 6: ...40 3 21 3 ROM Straps for Add in Card Design 40 Chapter 4 Timing Specifications 43 4 1 SMBus Timing 43 4 1 1 SMBus Write Cycle 43 4 1 2 SMBus Read Cycle 45 4 1 3 SMBus Read Thermal Sensor 46 4 2 Initi...

Page 7: ...Vega 10 Physical Dimensions 69 7 2 Pressure Specification 73 7 3 Board Solder Reflow Process Recommendations 73 7 3 1 Stencil Opening Size for Solderball Pads on PCB 73 7 3 2 FCBGA Reference Reflow Pr...

Page 8: ...viii Vega 10 Databook 56006_1 00 2017 Advanced Micro Devices Inc AMD Confidential Do not duplicate...

Page 9: ...tics Figure 5 1 Load Insertion Legend 60 Figure 5 2 Load Release Legend 60 Chapter 7 Mechanical Data Figure 7 1 Vega 10 Package Outline Preliminary MOD 00370 REV 01 70 Figure 7 2 Vega 10 Package Outli...

Page 10: ...x Vega 10 Databook 56006_1 00 2017 Advanced Micro Devices Inc AMD Confidential Do not duplicate...

Page 11: ...26 Table 3 10 General Purpose I O Interface 27 Table 3 11 AMD SVI2 Master Interface 29 Table 3 12 Panel Control Interface 29 Table 3 13 Global Swap Lock on Multiple GPUs 30 Table 3 14 Display Identifi...

Page 12: ...r DDC I2C Pins 62 Table 5 8 DisplayPort AUX Electrical Specification 62 Table 5 9 DisplayPort Main Link Electrical Specification 63 Table 5 10 Transmitter Electrical Specification 63 Table 5 11 Receiv...

Page 13: ...nd advisories as they identify amendments to the specifications in this databook Contact your local AMD support person for the software support schedules of GPU features 1 1 Part Identification 1 1 1...

Page 14: ...mples ES is found after the date code 2 Country of origin XXXXXX The assembly site such as USA SINGAPORE TAIWAN and CHINA 3 The part number Refer to Table 1 1 p 1 4 GPU Pin 1 Dot The branding format c...

Page 15: ...ode p 16 Logo Compliance p 17 Test Capability Features p 17 Other Features p 17 Export Control Classification p 18 2 1 Memory Interface 2 1 1 Memory Configurations Support Vega 10 adopts second genera...

Page 16: ...erent from the physical memory size that the AMD display driver reports to the operating system and control panel It does not limit the GPU s ability to use the entire frame buffer memory at any time...

Page 17: ...g static and dynamic branching High dynamic range rendering with floating point blending texture filtering and anti aliasing support 16 and 32 bit floating point components for high dynamic range comp...

Page 18: ...8 bit pixel texture are supported Programmable arbitration logic maximizes memory efficiency and is software upgradeable Fully associative texture color and z cache design Hierarchical z and stencil b...

Page 19: ...ink DVI Up to six 1920 1200 60 Hz Advanced video capabilities including high fidelity gamma color correction and scaling for High Dynamic Range HDR or Standard Dynamic Range SDR A high precision color...

Page 20: ...ly configured to any of single link DVI HDMI DisplayPort DP or embedded DisplayPort Vega 10 also supports dual link DVI Contact AMD if the design requires native dual link DVI support See Table 3 5 p...

Page 21: ...Maximum PCM Audio Channels 8 Maximum PCM Audio Bandwidth rate bits channels Mbps 36 864 Compressed audio Capabilities Maximum Compressed audio Bandwidth Mbps 24 576 Specific non PCM Audio format Suppo...

Page 22: ...ded Supports AMD FreeSync technology which dynamically synchronizes the refresh rate of a display with the frame rate of the GPU Based on DisplayPort Adaptive Sync technology Requires at least one dis...

Page 23: ...mings 594 MP sec 4096 2160 60 Hz 24 bpp or 30 bpp is supported using CTA timings 594 MP sec 2560 1440 144 Hz 24 bpp is supported using CTA timings 586 586 MP sec Examples of supported pixel rate resol...

Page 24: ...0 4 0 5 1 6 1 and 7 1 Sample rates 32 44 1 48 88 2 96 176 4 and 192 kHz Bits per sample 16 20 and 24 Non HBR compressed audio pass through up to 6 144 Mbps Supports AC 3 MPEG1 MP3 MPEG1 layer 3 MPEG2...

Page 25: ...ps Up to a bit rate of 160 Mbps Supports MVC decode for Blu ray 3D content Supports up to 18 HD streams 1080p at 30 fps each VC 1 Decode Implementation based on the SMPTE 421M specification Supports u...

Page 26: ...ptive and vector based deinterlacing filter eliminates video artifacts caused by displaying interlaced video on non interlaced displays analyzing the image and using the optimal deinterlacing function...

Page 27: ...r Management DPM defines multiple power levels for different clock and voltage domains to achieve best overall performance and idle power DPM includes intelligent firmware control to operate the diffe...

Page 28: ...lation frequency between 30 kHz and 33 kHz 2 9 Internal Thermal Sensor Vega 10 has an integrated thermal sensor that offers the following advantages Provides GPU die temperature accuracy 3 without the...

Page 29: ...lementation on the digital core logic which provides high fault coverage through ATPG automatic test pattern generation vectors covers both the stuck at and at speed transition fault Dedicated test lo...

Page 30: ...tion For information on the export control classification of this product please contact dl exportcontrol amd com 18 Functional Overview Vega 10 Databook 56006_1 00 2017 Advanced Micro Devices Inc AMD...

Page 31: ...is used For example QSA_ 7 0 means pins QSA_7 to QSA_0 In the Vega 10 pin assignment NC or NC_ Pins marked as NC are free pins that have no electrical connection on the GPU package RSVD These pins sho...

Page 32: ...SS VDDCR_ SOC VDDCR_ SOC VSS AB VSS TX5P_DP C0P TX5M_D PC0N VSS VDD_18 VDD_18 VSS TDO TDI RSVD VSS VSS VDDCR_ SOC VDDCR_ SOC VSS VSS VDDCR_ SOC VDDCR_ SOC VSS VSS VDDCR_ SOC VDDCR_ SOC VSS AC TXCBP_D...

Page 33: ...AB VDDCR_ SOC VDDCR_ SOC VDDCR_ SOC VDDCR_ SOC VDDCR_ SOC VDDCR_ SOC VDDCR_ SOC VDDCR_ SOC VDDCR_ SOC VDDCR_ SOC VDDCR_ SOC VDDCR_ SOC VDDCR_ SOC VDDCR_ SOC DFTIO_3 34 DFTIO_3 26 DFTIO_3 19 VDDCR_ SO...

Page 34: ...ial serial data transmitted up to 8 0 GT s bit rate PCIE_RX 15 0 P N I PCI Express receiver input data channel RX 15 0 Differential serial data received up to 8 0 GT s bit rate PCIE_ZVSS I O Connect t...

Page 35: ...DPD3P N Single link DisplayPort TMDS TX 5 3 P M_DPE 0 2 P N TXCEP M_DPE3P N Single link DisplayPort TMDS TX 2 0 P M_DPF 0 2 P N TXCFP M_DPF3P N Single link DisplayPort TMDS 3 5 Integrated HDMI TMDS In...

Page 36: ...signal line One FET is needed to disconnect the path from the 500 resistors to ground when the system is off and the panel is on DDC 2 1 CLK DDC 2 1 DATA DDCAUX 6 3 N DDCAUX 6 3 P I O Differential si...

Page 37: ...s a DisplayPort link A 100 nF capacitor is required on each differential signal placed near the connector TX 5 3 P M_DPE 0 2 P N TXCEP M_DPE3P N O DisplayPort DPE differential signals DPE can be confi...

Page 38: ...o identify the appropriate ROM type See Configuration Straps p 37 Table 3 9 Serial Flash Interface Pin Name Type PD PU Description GPIO_9_ROMSO I VDDAN_33 PD reset Serial ROM output from ROM General p...

Page 39: ...used as an alternative input for VRHOT interrupt to the GPU indicating thermal overload of the regulator Can be unconnected if not used GPIO_7_ROMSCK I O 3 3V VDDAN_33 PD reset For designs that have d...

Page 40: ...strap definition GPIO_19 I O 3 3V VDDAN_33 PD reset General purpose I O and pin strap See Table 3 24 p 38 for pin strap definition GPIO_20 I O 3 3V VDDAN_33 PD reset Do not connect on the PCB Provide...

Page 41: ...the SVI2 regulator is 0 9 V controlled by the GPU overwriting of boot VID on the PCB is not allowed If the second domain of the SVI2 regulator is used to power a GPU rail e g VDDCR_HBM VDDIO_MEM that...

Page 42: ...to update at the same time and have synchronous left right stereo timing In a multiple GPU design where displays are connected to more than one GPU connect SWAPLOCKA from all GPUs together with an ex...

Page 43: ...to AUX2P for use on one DisplayPort connector see reference schematics Note Can be unconnected if not used For the DDC functionality DDC data and clock signals I2 C master These pins can be used to s...

Page 44: ...be left floating or tied to 1 8 V through a 10 k resistor for normal GPU operation Must be accessible on all PCBs through a test point or resistor pad TCK I 1 8 V VDDAN_18 TCK test clock This pin can...

Page 45: ...on the PCB PLLCHARZ1_L PLLCHARZ1_H Each of the two balls should be connected to a capacitor 0 1 F in series with a resistor 51 1 to ground 3 16 Thermal Information and Management Interface Table 3 17...

Page 46: ...ed designs ALERT_L I O For debug purposes Not connected on the PCB PUMPIN I Pump speed input from the liquid cooled solution Regular 3 3 V TACH input PUMPOUT O Pump speed control output to the liquid...

Page 47: ...ull up resistor to 3 3 V and a pull down resistor to GND for each pin on the PCB By default install only pull up resistors on OSC_GAIN 2 1 and install only pull down resistor on OSC_GAIN 0 Note Both t...

Page 48: ...egulator If unused connect to test point or leave unconnected FB_VDDIO_MEM_HBM Provides VDDIO_MEM feedback path from DRAM to the regulator If unused connect to test point or leave unconnected VDDCR_HB...

Page 49: ...be connected to the 1 8 V power rail through pull up resistors for normal operation TS_A I O VDD_18 Not connected on the PCB Provide test pad GENERICA B I O VDDAN_33 General purpose I O or open drain...

Page 50: ...GND on the PCB for PINSTRAP_2 Provide a pull up resistor option to 1 8 V on the PCB for PINSTRAP_1 Provide a pull down resistor option to GND on the PCB for PINSTRAP_0 BIOS_ROM_EN GPIO_10 VDDAN_33 En...

Page 51: ...oints should be disabled 111 No usable endpoints 110 One usable endpoint 101 Two usable endpoints 100 Three usable endpoints 011 Four usable endpoints 010 Five usable endpoints 001 Six usable endpoint...

Page 52: ...LKREQB power management capability is enabled 0 Internal pull down Design dependent Provide a pull up resistor option to 1 8 V on the PCB BIF_LC_TX_SWING GPIO_13 VDDAN_33 Controls the transmitter full...

Page 53: ...D for the secondary display function F1 is the set to the same value as the primary display function F0 with bit 0 inverted 0 B0 Bits 4 to 19 STRAP_BIF_STRAP_MEM_AP_SIZE_DEV0_F0 Size of the primary me...

Page 54: ...IF_STRAP_VGA_DIS_DEV0_F0 VGA Disable determines whether or not the card will be recognized as the system s VGA controller via the SUBCLASS field in the PCI configuration space 0 VGA Controller capacit...

Page 55: ...h PWM p 52 4 1 SMBus Timing 4 1 1 SMBus Write Cycle The following figure shows an SRBM system register bus manager write cycle on the SMBus interface Figure 4 1 SMBus Write Cycle A typical SMBus write...

Page 56: ...MBus master issues a START bit to the slave b The SMBus master issues a 7 bit slave address to the slave c The SMBus master issues a write bit to the slave d The SMBus slave acknowledges the master e...

Page 57: ...e SMBus slave acknowledges the master i The SMBus master issues a 4 bit byte enable with a 4 bit zero padding These bits should have no effect on the reads j The SMBus slave acknowledges the master k...

Page 58: ...ster h The SMBus master acknowledges the slave i The SMBus slave sends SMB_RD_DATA 23 16 to the master j The SMBus master acknowledges the slave k The SMBus slave sends SMB_RD_DATA 15 8 to the master...

Page 59: ...s are forwarded to PHY 8 In parallel a If GPU memory repair is required then memory repair starts b eFuse and ROM straps are forwarded to other blocks in the GPU 9 Wait for memory repair to complete D...

Page 60: ...N A 100 ms TRST SEQ B The time the system software must wait after de assertion of PERSTB before accessing the GPU s PCI configuration space 100 ms Not limited TRAMP DOWN Power rail ramp down time 0 m...

Page 61: ...re are a total of 33 DWORDs of ROM based straps which are stored at byte locations 0x70 through 0xF4 in the serial flash memory See Table 3 25 p 41 for details For Vega 10 security features have been...

Page 62: ...ming Parameters for the Bootup Case Symbol Description Min ns Max ns Tcss ROMCSb falling edge to first clock sent to the device 110 Tsck ROMSCK period 70 Twl ROMSCK low time 30 Twh ROMSCK high time 30...

Page 63: ...HPD high and Aux Software controlled T4 Delay from HPD high to link training initialization Software controlled T8 Delay from Valid Video Data to ENA_BL VARY_BL active Software controlled T9 Delay fro...

Page 64: ...4 5 LCD Panel Backlight Control with PWM Figure 4 6 Backlight PWM Parameters 52 Timing Specifications Vega 10 Databook 56006_1 00 2017 Advanced Micro Devices Inc AMD Confidential Do not duplicate...

Page 65: ...of the BL_PWM_PERIOD register used to represent the backlight period The second purpose of this register is to specify how many MSBs of the BL_ACTIVE_INT_FRAC_CNT register field represent the integer...

Page 66: ...OD_BITCNT MSBs of this register field represent the integer component of the active duty cycle This applies regardless of whether fractional active duty mode BL_PWM_FRACTIONAL_EN is enabled or disable...

Page 67: ...ence clock frequency typically 27 or 54 MHz BL_PWM_REF_DIV is a 16 bit value specifying the division factor for this input reference clock BL_PWM_PERIOD is a 16 bit value representing the period of th...

Page 68: ...56 Timing Specifications Vega 10 Databook 56006_1 00 2017 Advanced Micro Devices Inc AMD Confidential Do not duplicate...

Page 69: ...1 Maximum Voltage Note In the below table the VDDCR_SOC voltage and VDDCR_HBM VDDIO_MEM voltage are defined as the command voltage sent by the GPU to the SVI2 voltage regulator through SVD data packet...

Page 70: ...lator powers VDDIO_MEM VDDCR_HBM rails Contact AMD for guidance on setting the second domain voltage to meet HBM power up requirements All voltage regulators that are compliant with AMD s SVI2 specifi...

Page 71: ...eedback loop of the switching regulator The filter inductor should be of 0 24 H and its DCR should be of 15 m or less The LDO solution does not need the filter inductor 6 For the switching regulator t...

Page 72: ...in addition to a 300 A steady state load Figure 5 2 Load Release Legend Table 5 4 Load Release Behavior Current Step Load A di dt A us Max Overshoot mV Max Settling Time us 3201 3656 76 21 Note If usi...

Page 73: ...provides the electrical characteristics of the TTL Interface GPIOs Table 5 5 DC Characteristics for 3 3 V GPIO Pads Parameter Condition Min Max Unit Notes VIL input voltage low level Maximum DC volta...

Page 74: ...I2C_Y_VIH DC Minimum DC voltage at the PAD pin that will produce a stable high at the I2C_Y pin of the macro 2 3 V 1 I2C_Y_VIL DC Maximum DC voltage at the PAD pin that will produce a stable low at t...

Page 75: ...ta of pre emphasis level 1 versus level 0 2 0 dB Delta of pre emphasis level 2 versus level 1 1 6 dB VTX PREEMP OFF Maximum pre emphasis when disabled 0 25 dB 5 8 SMBus Electrical Characteristics The...

Page 76: ...e 40 60 2 YtiPDr Receiver propagation delay rise 400 ns 1 2 4 YtiPDf Receiver propagation delay fall 20 ns 1 2 4 1 Measured with an edge rate of 1 s at the PAD pin 2 Assuming perfect duty cycle on inp...

Page 77: ...istics Table 6 2 Thermal Characteristics Variable Value Tj op Maximum recommended operating temperature This is the maximum temperature at which the functionality is qualified and tested Operation abo...

Page 78: ...te The data are targets only and are subject to change Table 6 3 TGP for Discrete Variants Variant Vega 10 XTX VDDCR_SOC V 0 80 1 25 VDDCI_MEM V 0 90 VDDCR_HBM VDDIO_MEM V 1 35 DPM Level GFXCLK MHz SO...

Page 79: ...emperature the external thermal sensor chip must support and enable beta compensation 6 5 Storage Requirements Ambient temperature 40 to 70 Relative humidity 0 to 90 Thermal Data 67 2017 Advanced Micr...

Page 80: ...68 Thermal Data Vega 10 Databook 56006_1 00 2017 Advanced Micro Devices Inc AMD Confidential Do not duplicate...

Page 81: ...llowing list of linked cross references Physical Dimensions p 69 Pressure Specification p 73 Board Solder Reflow Process Recommendations p 73 7 1 Physical Dimensions 7 1 1 Vega 10 Physical Dimensions...

Page 82: ...Figure 7 1 Vega 10 Package Outline Preliminary MOD 00370 REV 01 70 Mechanical Data Vega 10 Databook 56006_1 00 2017 Advanced Micro Devices Inc AMD Confidential Do not duplicate...

Page 83: ...Figure 7 2 Vega 10 Package Outline Preliminary MOD 00370 REV 01 Top View Mechanical Data 71 2017 Advanced Micro Devices Inc AMD Confidential Do not duplicate Vega 10 Databook 56006_1 00...

Page 84: ...Figure 7 3 Vega 10 Ball Names Bottom View 72 Mechanical Data Vega 10 Databook 56006_1 00 2017 Advanced Micro Devices Inc AMD Confidential Do not duplicate...

Page 85: ...package will not exceed 600 micron strain under any circumstance For strain gauge setup and test methodology refer to industrial standards IPC JEDEC 9704 Printed Wiring Board Strain Gauge Test Guideli...

Page 86: ...d To ensure that the reflow profile meets the target specification on both sides of SMT components a different reflow profile for the first and second reflow may be required A mechanical stiffening ca...

Page 87: ...four minutes Soaking Time 130 to 170 Typically 60 to 80 seconds Liquidus 220 Typically 60 to 80 seconds Ramp Rate Ramp up Ramp down 2 second 1 second Peak Maximum 245 235 5 Temperature at Peak Within...

Page 88: ...76 Mechanical Data Vega 10 Databook 56006_1 00 2017 Advanced Micro Devices Inc AMD Confidential Do not duplicate...

Page 89: ...s BYPASS EXTEST and PRELOAD instructions A BSDL file for each of the modes can be obtained from the AMD OEM Resource Center 8 2 Boundary Scan The Vega 10 boundary scan can perform board level capture...

Page 90: ...K rise 20 ns tbsdv TCK low to output data valid 0 00 s 0 05 s ttcst TDI TMS setup time to TCK rise 2 5 ns ttcht TDI TMS hold time to TCK rise 3 0 ns ttcdv TCK low to TDO data valid 0 0 s 0 05 s Figure...

Page 91: ...by Ball Reference Ball Reference Signal Name A2 VDDCR_SOC A3 VDDCR_SOC A4 VDDCR_SOC A6 VDDCR_SOC A7 VDDCR_SOC A8 VDDCR_SOC A9 VDDCR_SOC A10 VDDCR_SOC A11 VDDCR_SOC A12 VDDCR_SOC A13 VDDCR_SOC A14 VDD...

Page 92: ...RSVD B2 DFTIO_29 B3 VSS B4 DFTIO_44 B5 DFTIO_31 B6 DFTIO_48 B7 VSS B8 DFTIO_58 B9 DFTIO_68 B10 VDDCR_SOC B11 VSS B12 RSVD B13 DFTIO_86 B14 DFTIO_91 B15 VDDCR_SOC B16 DFTIO_97 B17 DFTIO_107 B18 DFTIO_...

Page 93: ...209 B43 VSS B44 DFTIO_187 B45 VDDCR_SOC C1 DFTIO_17 C2 DFTIO_9 C3 DFTIO_21 C4 DFTIO_22 C5 VSS C6 DFTIO_32 C7 DFTIO_49 C8 DFTIO_52 C9 VSS C10 DFTIO_75 C11 DFTIO_87 C12 RSVD C13 VSS C14 DFTIO_74 C15 DFT...

Page 94: ...C41 VSS C42 DFTIO_204 C43 DFTIO_182 C44 DFTIO_189 C45 VDDCR_SOC D1 VSS D2 DFTIO_18 D3 DFTIO_27 D4 DFTIO_13 D5 DFTIO_33 D6 DFTIO_39 D7 VSS D8 DFTIO_36 D9 DFTIO_47 D10 DFTIO_70 D11 VSS D12 RSVD D13 DFT...

Page 95: ...IO_149 D37 DFTIO_181 D38 DFTIO_164 D39 VSS D40 DFTIO_172 D41 DFTIO_192 D42 DFTIO_180 D43 VSS D44 DFTIO_186 D45 VDDCR_SOC E2 VSS E3 DFTIO_5 E4 DFTIO_2 E5 VSS E6 DFTIO_12 E7 DFTIO_16 E8 DFTIO_34 E9 VSS...

Page 96: ...14 E36 DFTIO_221 E37 VSS E38 DFTIO_219 E39 DFTIO_216 E40 DFTIO_228 E41 VSS E42 DFTIO_194 E43 DFTIO_199 E44 DFTIO_188 F1 VSS F2 TXCFP_DPF3P F3 TXCFM_DPF3N F4 VSS F5 DDC1DATA F6 DDC1CLK F7 VSS F8 DFTIO_...

Page 97: ..._185 F33 DFTIO_220 F34 DFTIO_206 F35 VDDCR_SOC F36 DFTIO_254 F37 DFTIO_243 F38 DFTIO_235 F39 VSS F40 DFTIO_200 F41 DFTIO_229 F42 DFTIO_195 F43 VSS F44 DFTIO_215 F45 VDDCR_SOC G1 TX0P_DPF2P G2 TX0M_DPF...

Page 98: ...G31 DFTIO_156 G32 DFTIO_212 G33 VSS G34 DFTIO_252 G35 DFTIO_234 G36 DFTIO_227 G37 VSS G38 DFTIO_257 G39 DFTIO_245 G40 DFTIO_244 G41 VSS G42 DFTIO_223 G43 DFTIO_224 G44 DFTIO_205 G45 VDDCR_SOC H1 VSS H...

Page 99: ...DFTIO_178 H29 DFTIO_191 H30 DFTIO_198 H31 VDDCR_SOC H32 DFTIO_290 H33 DFTIO_281 H34 DFTIO_238 H35 VDDCR_SOC H36 DFTIO_218 H37 DFTIO_207 H38 DFTIO_269 H39 VDDCR_SOC H40 DFTIO_272 H41 DFTIO_249 H42 DFTI...

Page 100: ...5 VDDCR_SOC J26 DFTIO_124 J27 DFTIO_140 J28 DFTIO_184 J29 VDDCR_SOC J30 DFTIO_197 J31 DFTIO_213 J32 DFTIO_232 J33 VDDCR_SOC J34 DFTIO_247 J35 DFTIO_193 J36 DFTIO_255 J37 VSS J38 DFTIO_264 J39 DFTIO_25...

Page 101: ...K23 VSS K24 VSS K25 VDDCR_SOC K26 VDDCR_SOC K27 VSS K28 VSS K29 VDDCR_SOC K30 VDDCR_SOC K31 VSS K32 VSS K33 VDDCR_SOC K34 VDDCR_SOC K35 VSS K36 VSS K37 DFTIO_265 K38 DFTIO_286 K39 VDDCR_SOC K40 DFTIO...

Page 102: ...L21 VDDCR_SOC L22 VDDCR_SOC L23 VSS L24 VSS L25 VDDCR_SOC L26 VDDCR_SOC L27 VSS L28 VSS L29 VDDCR_SOC L30 VDDCR_SOC L31 VSS L32 VSS L33 VDDCR_SOC L34 VDDCR_SOC L35 VDDCR_SOC L36 VDDCR_SOC L37 VDDCR_S...

Page 103: ...17 VDDCR_SOC M18 VDDCR_SOC M19 VSS M20 VSS M21 VDDCR_SOC M22 VDDCR_SOC M23 VSS M24 VSS M25 VDDCR_SOC M26 VDDCR_SOC M27 VSS M28 VSS M29 VDDCR_SOC M30 VDDCR_SOC M31 VSS M32 VSS M33 VDDCR_SOC M34 VDDCR_S...

Page 104: ...VD N12 VSS N13 VDDCR_SOC N14 VDDCR_SOC N15 VSS N16 VSS N17 VDDCR_SOC N18 VDDCR_SOC N19 VSS N20 VSS N21 VDDCR_SOC N22 VDDCR_SOC N23 VSS N24 VSS N25 VDDCR_SOC N26 VDDCR_SOC N27 VSS N28 VSS N29 VDDCR_SOC...

Page 105: ...8 RSVD P9 DFTIO_15 P10 RSVD P11 VSS P12 VSS P13 VDDCR_SOC P14 VDDCR_SOC P15 VSS P16 VSS P17 VDDCR_SOC P18 VDDCR_SOC P19 VSS P20 VSS P21 VDDCR_SOC P22 VDDCR_SOC P23 VSS P24 VSS P25 VDDCR_SOC P26 VDDCR_...

Page 106: ...R6 VSS R7 GENLK_CLK R8 GENLK_VSYNC R9 VSS R10 RSVD R11 RSVD R12 VSS R13 VDDCR_SOC R14 VDDCR_SOC R15 VSS R16 VSS R17 VDDCR_SOC R18 VDDCR_SOC R19 VSS R20 VSS R21 VDDCR_SOC R22 VDDCR_SOC R23 VSS R24 VSS...

Page 107: ...T2 TX0P_DPD2P T3 TX0M_DPD2N T4 VSS T5 SWAPLOCKA T6 SWAPLOCKB T7 VSS T8 GPIO_0 T9 GPIO_SVD0 T10 RSVD T11 VSS T12 VSS T13 VDDCR_SOC T14 VDDCR_SOC T15 VSS T16 VSS T17 VDDCR_SOC T18 VDDCR_SOC T19 VSS T20...

Page 108: ...SOC T44 DFTIO_285 T45 VDDCR_SOC U1 TX1P_DPD1P U2 TX1M_DPD1N U3 VSS U4 RSVD U5 RSVD U6 VSS U7 GPIO_1 U8 GPIO_SVT0 U9 VSS U10 RSVD U11 RSVD U12 VSS U13 VDDCR_SOC U14 VDDCR_SOC U15 VSS U16 VSS U17 VDDCR_...

Page 109: ...DFTIO_296 U45 VDDCR_SOC V1 VSS V2 TX2P_DPD0P V3 TX2M_DPD0N V4 VSS V5 GENERICE_HPD4 V6 GPIO_9_ROMSO V7 GPIO_2 V8 VSS V9 GPIO_SVC0 V10 INTCRACKMONGLL V11 VSS V12 VSS V13 VDDCR_SOC V14 VDDCR_SOC V15 VSS...

Page 110: ...V41 DFTIO_273 V42 DFTIO_274 V43 VSS V44 DFTIO_266 V45 VDDCR_SOC W1 TXCCP_DPC3P W2 TXCCM_DPC3N W3 VSS W4 DDCAUX4P W5 DDCAUX4N W6 VSS W7 GPIO_7_ROMSCK W8 GPIO_8_ROMSI W9 VSS W10 RSVD W11 RSVD W12 VSS W...

Page 111: ...DCR_SOC W37 VDDCR_SOC W38 DFTIO_291 W39 DFTIO_292 W40 DFTIO_293 W41 VDDCR_SOC W42 DFTIO_304 W43 DFTIO_306 W44 DFTIO_297 W45 VDDCR_SOC Y1 VSS Y2 TX3P_DPC2P Y3 TX3M_DPC2N Y4 VSS Y5 VDD_18 Y6 VDD_18 Y7 G...

Page 112: ...DDCR_SOC Y35 VDDCR_SOC Y36 VDDCR_SOC Y37 INTCRACKMONGUR Y38 DFTIO_294 Y39 VDDCR_SOC Y40 DFTIO_316 Y41 DFTIO_323 Y42 DFTIO_305 Y43 VDDCR_SOC Y44 DFTIO_302 Y45 VDDCR_SOC AA1 TX4P_DPC1P AA2 TX4M_DPC1N AA...

Page 113: ...31 VSS AA32 VSS AA33 VSS AA34 VSS AA35 VSS AA36 VSS AA37 VSS AA38 DFTIO_329 AA39 DFTIO_318 AA40 DFTIO_321 AA41 VSS AA42 DFTIO_312 AA43 DFTIO_313 AA44 DFTIO_307 AA45 VDDCR_SOC AB1 VSS AB2 TX5P_DPC0P AB...

Page 114: ...AB28 VSS AB29 VSS AB30 VSS AB31 VSS AB32 VSS AB33 VSS AB34 VSS AB35 VSS AB36 VSS AB37 DFTIO_332 AB38 DFTIO_335 AB39 VSS AB40 DFTIO_317 AB41 DFTIO_314 AB42 DFTIO_325 AB43 VSS AB44 DFTIO_311 AB45 VDDCR_...

Page 115: ...27 VDDCR_SOC AC28 VDDCR_SOC AC29 VDDCR_SOC AC30 VDDCR_SOC AC31 VDDCR_SOC AC32 VDDCR_SOC AC33 VDDCR_SOC AC34 VDDCR_SOC AC35 VDDCR_SOC AC36 VDDCR_SOC AC37 VDDCR_SOC AC38 DFTIO_334 AC39 DFTIO_326 AC40 DF...

Page 116: ...DDCR_SOC AD25 VDDCR_SOC AD26 VDDCR_SOC AD27 VDDCR_SOC AD28 VDDCR_SOC AD29 VDDCR_SOC AD30 VDDCR_SOC AD31 VDDCR_SOC AD32 VDDCR_SOC AD33 VDDCR_SOC AD34 VDDCR_SOC AD35 VDDCR_SOC AD36 VDDCR_SOC AD37 RSVD A...

Page 117: ...VSS AE17 VDDCR_SOC AE18 VDDCR_SOC AE19 VSS AE20 VSS AE21 VSS AE22 VSS AE23 VSS AE24 VSS AE25 VSS AE26 VSS AE27 VSS AE28 VSS AE29 VSS AE30 VSS AE31 VSS AE32 VSS AE33 VSS AE34 VSS AE35 VSS AE36 VSS AE37...

Page 118: ...F13 VSS AF14 VSS AF15 VSS AF16 VSS AF17 VDDCR_SOC AF18 VDDCR_SOC AF19 VSS AF20 VSS AF21 VSS AF22 VSS AF23 VSS AF24 VSS AF25 VSS AF26 VSS AF27 VSS AF28 VSS AF29 VSS AF30 VSS AF31 VSS AF32 VSS AF33 VSS...

Page 119: ...AG16 VSS AG17 VDDCR_SOC AG18 VDDCR_SOC AG19 VDDCR_SOC AG20 VDDCR_SOC AG21 VDDCR_SOC AG22 VDDCR_SOC AG23 VDDCR_SOC AG24 VDDCR_SOC AG25 VDDCR_SOC AG26 VDDCR_SOC AG27 VDDCR_SOC AG28 VDDCR_SOC AG29 VDDCR...

Page 120: ...VSS AH13 VSS AH14 VSS AH15 VSS AH16 VSS AH17 FB_VDDCR_SOC AH18 VDDCR_SOC AH19 VDDCR_SOC AH20 VDDCR_SOC AH21 VDDCR_SOC AH22 VDDCR_SOC AH23 VDDCR_SOC AH24 VDDCR_SOC AH25 VDDCR_SOC AH26 VDDCR_SOC AH27 V...

Page 121: ...RSVD AJ9 VSS AJ10 RSVD AJ11 TEST_PG AJ12 VSS AJ13 VSS AJ14 RSVD AJ15 HBMA_DAP_49 AJ16 FB_VSS_A AJ17 HBMA_DAP_32 AJ18 HBMA_DAP_28 AJ19 VSS AJ20 HBMA_DAP_12 AJ21 HBMA_DAP_7 AJ22 VSS AJ23 HBMA_DAP_17 AJ2...

Page 122: ...PCIE_ZVSS AK6 VSS AK7 RSVD AK8 VDD_080_EFUSE AK9 VDD_080_EFUSE AK10 RSVD AK11 VSS AK12 VSS AK13 VSS AK14 HBMA_DAP_59 AK15 HBMA_DAP_46 AK16 FB_VDDCI_MEM AK17 HBMA_DAP_38 AK18 VSS AK19 HBMA_DAP_23 AK20...

Page 123: ...VSS AL2 GENERICA AL3 VSS AL4 GPIO_11 AL5 GPIO_12 AL6 RSVD AL7 VDD_080 AL8 RSVD AL9 VSS AL10 TS_A AL11 RSVD AL12 VSS AL13 VSS AL14 HBMA_DAP_58 AL15 RSVD AL16 VSS AL17 VDDCI_MEM AL18 HBMA_DAP_26 AL19 HB...

Page 124: ...R_SOC AL42 DFTIO_369 AL43 DFTIO_373 AL44 DFTIO_380 AL45 VDDCR_SOC AM1 XTALIN AM2 VSS AM3 XTALOUT AM4 VSS AM5 GPIO_14 AM6 GPIO_13 AM7 VSS AM8 VDD_080 AM9 DBREQ_L AM10 SDA AM11 VSS AM12 VSS AM13 VSS AM1...

Page 125: ...SVD AM38 RSVD AM39 VDDCR_SOC AM40 DFTIO_336 AM41 DFTIO_372 AM42 DFTIO_337 AM43 VDDCR_SOC AM44 VDDCR_SOC AM45 VDDCR_SOC AN1 RSVD AN2 RSVD AN3 RSVD AN4 RSVD AN5 RSVD AN6 RSVD AN7 VSS AN8 RSVD AN9 VSS AN...

Page 126: ...P_6 AN36 VSS AN37 MTESTB AN38 RSVD AN39 DFTIO_363 AN40 DFTIO_368 AN41 VSS AN42 DFTIO_339 AN43 VDDCR_SOC AN44 VDDCR_SOC AN45 VDDCR_SOC AP1 OSC_GAIN0 AP2 OSC_GAIN1 AP3 OSC_GAIN2 AP4 RSVD AP5 RSVD AP6 RS...

Page 127: ...CR_HBM AP34 HBMB_DAP_22 AP35 VSS AP36 HBMB_DAP_2 AP37 HBMB_DAP_5 AP38 RSVD AP39 DFTIO_379 AP40 DFTIO_374 AP41 DFTIO_375 AP42 VDDCR_SOC AP43 VDDCR_SOC AP44 VDDCR_SOC AP45 VDDCR_SOC AR1 BP_0 AR2 BP_1 AR...

Page 128: ...49 AR30 HBMB_DAP_42 AR31 VDDIO_MEM AR32 HBMB_DAP_32 AR33 HBMB_DAP_28 AR34 VDDCR_HBM AR35 HBMB_DAP_9 AR36 VREFEXTB AR37 RSVD AR38 RSVD AR39 DFTIO_364 AR40 DFTIO_365 AR41 VDDCR_SOC AR42 VDDCR_SOC AR43 V...

Page 129: ...O_MEM AT28 HBMB_DAP_57 AT29 HBMB_DAP_52 AT30 VDDIO_MEM AT31 HBMB_DAP_43 AT32 HBMB_DAP_26 AT33 VDDIO_MEM AT34 HBMB_DAP_18 AT35 HBMB_DAP_8 AT36 RSVD AT37 TEMPINRETURN AT38 VSS AT39 VDDCR_SOC AT40 VDDCR_...

Page 130: ...SS AU27 RSVD AU28 HBMB_DAP_56 AU29 VSS AU30 HBMB_DAP_46 AU31 HBMB_DAP_36 AU32 VSS AU33 HBMB_DAP_25 AU34 HBMB_DAP_12 AU35 VSS AU36 INTCRACKMONDB AU37 TEMPIN AU38 VDDCR_SOC AU39 VDDCR_SOC AU40 VDDCR_SOC...

Page 131: ...RSVD AV24 VDDIO_MEM AV25 VSS AV26 VDDIO_MEM AV27 VDDIO_MEM AV28 VSS AV29 HBMB_DAP_51 AV30 HBMB_DAP_40 AV31 VSS AV32 HBMB_DAP_34 AV33 HBMB_DAP_19 AV34 VSS AV35 HBMB_DAP_15 AV36 RSVD AV37 VSS AV38 RSVD...

Page 132: ...2 VSS AW23 RSVD AW24 RSVD AW25 VDDCR_HBM AW26 RSVD AW27 RSVD AW28 VDDCR_HBM AW29 RSVD AW30 VDDIO_MEM AW31 HBMB_DAP_35 AW32 HBMB_DAP_29 AW33 VDDIO_MEM AW34 HBMB_DAP_20 AW35 HBMB_DAP_4 AW36 VDDIO_MEM AW...

Page 133: ...AY17 PCIE_TX11P AY18 PCIE_TX11N AY19 VSS AY20 PCIE_TX14P AY21 PCIE_TX14N AY22 VSS AY23 RSVD AY24 VDDIO_MEM AY25 PLLCHARZ1_L AY26 PLLCHARZ1_H AY27 VDDCR_HBM AY28 FB_VSS_B AY29 FB_VDDIO_MEM_GPU AY30 RSV...

Page 134: ...TX7P BA14 PCIE_TX7N BA15 VSS BA16 PCIE_TX10P BA17 PCIE_TX10N BA18 VSS BA19 PCIE_TX13P BA20 PCIE_TX13N BA21 VSS BA22 VSS BA23 RSVD BA24 RSVD BA25 RSVD BA26 RSVD BA27 VSS BA28 FB_VDDIO_MEM_HBM BA29 FB_V...

Page 135: ...VSS BB12 PCIE_TX6P BB13 PCIE_TX6N BB14 VSS BB15 PCIE_TX9P BB16 PCIE_TX9N BB17 VSS BB18 PCIE_TX12P BB19 PCIE_TX12N BB20 VSS BB21 PCIE_TX15P BB22 PCIE_TX15N BB23 VSS BB24 RSVD BB25 RSVD BB26 RSVD BB27 R...

Page 136: ...X3N BC10 VSS BC11 PCIE_RX6P BC12 PCIE_RX6N BC13 VSS BC14 PCIE_RX9P BC15 PCIE_RX9N BC16 VSS BC17 PCIE_RX12P BC18 PCIE_RX12N BC19 VSS BC20 PCIE_RX15P BC21 PCIE_RX15N BC22 VSS BC23 RSVD BC24 RSVD BC25 VS...

Page 137: ...CIE_RX2P BD8 PCIE_RX2N BD9 VSS BD10 PCIE_RX5P BD11 PCIE_RX5N BD12 VSS BD13 PCIE_RX8P BD14 PCIE_RX8N BD15 VSS BD16 PCIE_RX11P BD17 PCIE_RX11N BD18 VSS BD19 PCIE_RX14P BD20 PCIE_RX14N BD21 VSS BD22 RSVD...

Page 138: ...1P BE7 PCIE_RX1N BE8 VSS BE9 PCIE_RX4P BE10 PCIE_RX4N BE11 VSS BE12 PCIE_RX7P BE13 PCIE_RX7N BE14 VSS BE15 PCIE_RX10P BE16 PCIE_RX10N BE17 VSS BE18 PCIE_RX13P BE19 PCIE_RX13N BE20 VSS BE21 VSS BE22 RE...

Page 139: ...Signal Name Signal Name Ball Reference ALERT_L BD31 ANALOGIO AJ7 AUX1N G5 AUX1P G4 AUX2N K3 AUX2P K2 AUX_ZVSS P5 BL_ENABLE AU14 BL_PWM_DIM AV16 BP_0 AR1 BP_1 AR2 BP_2 AT2 BP_3 AT1 CLKREQB BE3 CTF BE3...

Page 140: ...FTIO_9 C2 DFTIO_10 N10 DFTIO_11 M8 DFTIO_12 E6 DFTIO_13 D4 DFTIO_14 K9 DFTIO_15 P9 DFTIO_16 E7 DFTIO_17 C1 DFTIO_18 D2 DFTIO_19 K10 DFTIO_20 H8 DFTIO_21 C3 DFTIO_22 C4 DFTIO_23 K8 DFTIO_24 L10 DFTIO_2...

Page 141: ...J16 DFTIO_52 C8 DFTIO_53 F9 DFTIO_54 J15 DFTIO_55 E12 DFTIO_56 E11 DFTIO_57 G11 DFTIO_58 B8 DFTIO_59 H12 DFTIO_60 H16 DFTIO_61 F14 DFTIO_62 E14 DFTIO_63 G14 DFTIO_64 E10 DFTIO_65 D13 DFTIO_66 H20 DFT...

Page 142: ...IO_94 E18 DFTIO_95 F17 DFTIO_96 C18 DFTIO_97 B16 DFTIO_98 G20 DFTIO_99 J20 DFTIO_100 J19 DFTIO_101 D17 DFTIO_102 C19 DFTIO_103 F18 DFTIO_104 C20 DFTIO_105 D18 DFTIO_106 E22 DFTIO_107 B17 DFTIO_108 D20...

Page 143: ...4 DFTIO_136 B25 DFTIO_137 D28 DFTIO_138 F21 DFTIO_139 C28 DFTIO_140 J27 DFTIO_141 E24 DFTIO_142 D29 DFTIO_143 B26 DFTIO_144 G27 DFTIO_145 F24 DFTIO_146 D26 DFTIO_147 C32 DFTIO_148 E30 DFTIO_149 D36 DF...

Page 144: ...7 DFTIO_178 H28 DFTIO_179 D33 DFTIO_180 D42 DFTIO_181 D37 DFTIO_182 C43 DFTIO_183 F29 DFTIO_184 J28 DFTIO_185 F32 DFTIO_186 D44 DFTIO_187 B44 DFTIO_188 E44 DFTIO_189 C44 DFTIO_190 D34 DFTIO_191 H29 DF...

Page 145: ...8 DFTIO_220 F33 DFTIO_221 E36 DFTIO_222 C39 DFTIO_223 G42 DFTIO_224 G43 DFTIO_225 H44 DFTIO_226 H42 DFTIO_227 G36 DFTIO_228 E40 DFTIO_229 F41 DFTIO_230 J43 DFTIO_231 J44 DFTIO_232 J32 DFTIO_233 K44 DF...

Page 146: ...1 DFTIO_262 R43 DFTIO_263 R44 DFTIO_264 J38 DFTIO_265 K37 DFTIO_266 V44 DFTIO_267 P42 DFTIO_268 T42 DFTIO_269 H38 DFTIO_270 R39 DFTIO_271 U42 DFTIO_272 H40 DFTIO_273 V41 DFTIO_274 V42 DFTIO_275 M37 DF...

Page 147: ...O_304 W42 DFTIO_305 Y42 DFTIO_306 W43 DFTIO_307 AA44 DFTIO_308 U40 DFTIO_309 R40 DFTIO_310 M38 DFTIO_311 AB44 DFTIO_312 AA42 DFTIO_313 AA43 DFTIO_314 AB41 DFTIO_315 R38 DFTIO_316 Y40 DFTIO_317 AB40 DF...

Page 148: ...TIO_346 AY42 DFTIO_347 AW42 DFTIO_348 BA43 DFTIO_349 AW44 DFTIO_350 BA44 DFTIO_351 AY41 DFTIO_352 AW40 DFTIO_353 AY44 DFTIO_354 BA40 DFTIO_355 AT43 DFTIO_356 AV44 DFTIO_357 AU42 DFTIO_358 AU43 DFTIO_3...

Page 149: ...ZVSS AG6 FANIN BE29 FANOUT BD29 FB_VDDCI_MEM AK16 FB_VDDCR_HBM BA29 FB_VDDCR_SOC AH17 FB_VDDIO_MEM_GPU AY29 FB_VDDIO_MEM_HBM BA28 FB_VSS_A AJ16 FB_VSS_B AY28 GENERICA AL2 GENERICB AV14 GENERICC_HPD2 K...

Page 150: ...AP_1 AK26 HBMA_DAP_2 AR27 HBMA_DAP_3 AM27 HBMA_DAP_4 AM26 HBMA_DAP_5 AL27 HBMA_DAP_6 AJ26 HBMA_DAP_7 AJ21 HBMA_DAP_8 AJ24 HBMA_DAP_9 AK25 HBMA_DAP_10 AN26 HBMA_DAP_11 AL22 HBMA_DAP_12 AJ20 HBMA_DAP_13...

Page 151: ...P_41 AL19 HBMA_DAP_42 AN23 HBMA_DAP_43 AR17 HBMA_DAP_44 AR21 HBMA_DAP_45 AT22 HBMA_DAP_46 AK15 HBMA_DAP_47 AT20 HBMA_DAP_48 AT19 HBMA_DAP_49 AJ15 HBMA_DAP_50 AN19 HBMA_DAP_51 AN17 HBMA_DAP_52 AN15 HBM...

Page 152: ...AM33 HBMB_DAP_24 AJ33 HBMB_DAP_25 AU33 HBMB_DAP_26 AT32 HBMB_DAP_27 AM32 HBMB_DAP_28 AR33 HBMB_DAP_29 AW32 HBMB_DAP_30 AJ32 HBMB_DAP_31 AK32 HBMB_DAP_32 AR32 HBMB_DAP_33 AN32 HBMB_DAP_34 AV32 HBMB_DAP...

Page 153: ...RACKMONGLR Y10 INTCRACKMONGUL V37 INTCRACKMONGUR Y37 INTCRACKMONP BC43 INTCRACKMONPDG BC42 MACO_EN AT12 MTESTA AM15 MTESTB AN37 OSC_GAIN0 AP1 OSC_GAIN1 AP2 OSC_GAIN2 AP3 PCIE_REFCLKN AY6 PCIE_REFCLKP...

Page 154: ...D19 PCIE_RX15N BC21 PCIE_RX15P BC20 PCIE_TX0N BB7 PCIE_TX0P BB6 PCIE_TX1N BA8 PCIE_TX1P BA7 PCIE_TX2N AY9 PCIE_TX2P AY8 PCIE_TX3N BB10 PCIE_TX3P BB9 PCIE_TX4N BA11 PCIE_TX4P BA10 PCIE_TX5N AY12 PCIE_T...

Page 155: ...P_2 BB1 PINSTRAP_3 BA3 PINSTRAP_4 BA2 PINSTRAP_5 AY3 PINSTRAP_6 AY2 PINSTRAP_7 AY1 PLLCHARZ1_H AY26 PLLCHARZ1_L AY25 PROCHOT_L BC29 PUMPIN BE33 PUMPOUT BD33 PX_EN AU16 REFCLKN BE23 REFCLKP BE22 RSVD B...

Page 156: ...AD44 RSVD AE11 RSVD AE38 RSVD AE39 RSVD AE40 RSVD AE42 RSVD AE43 RSVD AE44 RSVD AF10 RSVD AF37 RSVD AF38 RSVD AF40 RSVD AF41 RSVD AF42 RSVD AF44 RSVD AG38 RSVD AG39 RSVD AG40 RSVD AG42 RSVD AG43 RSVD...

Page 157: ...8 RSVD AM14 RSVD AM37 RSVD AM38 RSVD AN1 RSVD AN2 RSVD AN3 RSVD AN4 RSVD AN5 RSVD AN6 RSVD AN8 RSVD AN11 RSVD AN12 RSVD AN14 RSVD AN38 RSVD AP4 RSVD AP5 RSVD AP6 RSVD AP9 RSVD AP10 RSVD AP38 RSVD AR8...

Page 158: ...AV2 RSVD AV3 RSVD AV8 RSVD AV12 RSVD AV13 RSVD AV18 RSVD AV19 RSVD AV20 RSVD AV21 RSVD AV22 RSVD AV23 RSVD AV36 RSVD AV38 RSVD AV39 RSVD AV45 RSVD AW1 RSVD AW2 RSVD AW7 RSVD AW10 RSVD AW12 RSVD AW13...

Page 159: ...VD BA30 RSVD BA32 RSVD BA35 RSVD BA36 RSVD BA38 RSVD BA39 RSVD BB24 RSVD BB25 RSVD BB26 RSVD BB27 RSVD BB31 RSVD BB32 RSVD BB37 RSVD BB38 RSVD BB40 RSVD BB41 RSVD BB43 RSVD BC3 RSVD BC23 RSVD BC24 RSV...

Page 160: ...VD BE36 RSVD BE38 RSVD BE40 SCL AN10 SDA AM10 SMBCLK BC2 SMBDAT BC1 SWAPLOCKA T5 SWAPLOCKB T6 TCK AC8 TDI AB9 TDO AB8 TEMPIN AU37 TEMPINRETURN AT37 TEST6 T37 TESTEN AD8 TEST_PG AJ11 TEST_PG_BACO AV15...

Page 161: ...A2P AH2 TX3P_DPC2P Y2 TX3P_DPE2P M2 TX4M_DPA1N AJ2 TX4M_DPC1N AA2 TX4M_DPE1N N2 TX4P_DPA1P AJ1 TX4P_DPC1P AA1 TX4P_DPE1P N1 TX5M_DPA0N AK3 TX5M_DPC0N AB3 TX5M_DPE0N P3 TX5P_DPA0P AK2 TX5P_DPC0P AB2 TX...

Page 162: ...32 VDDCI_MEM AL35 VDDCI_MEM AM19 VDDCI_MEM AM22 VDDCI_MEM AM25 VDDCI_MEM AM28 VDDCI_MEM AM31 VDDCI_MEM AM34 VDDCR_BACO AG10 VDDCR_BACO AG11 VDDCR_BACO AH9 VDDCR_BACO AH10 VDDCR_HBM AP18 VDDCR_HBM AP19...

Page 163: ...3 VDDCR_SOC A14 VDDCR_SOC A15 VDDCR_SOC A16 VDDCR_SOC A17 VDDCR_SOC A18 VDDCR_SOC A19 VDDCR_SOC A20 VDDCR_SOC A21 VDDCR_SOC A22 VDDCR_SOC A23 VDDCR_SOC A24 VDDCR_SOC A25 VDDCR_SOC A26 VDDCR_SOC A27 VD...

Page 164: ...3 VDDCR_SOC D27 VDDCR_SOC D31 VDDCR_SOC D35 VDDCR_SOC D45 VDDCR_SOC F15 VDDCR_SOC F19 VDDCR_SOC F23 VDDCR_SOC F27 VDDCR_SOC F31 VDDCR_SOC F35 VDDCR_SOC F45 VDDCR_SOC G45 VDDCR_SOC H15 VDDCR_SOC H19 VD...

Page 165: ...3 VDDCR_SOC K45 VDDCR_SOC L13 VDDCR_SOC L14 VDDCR_SOC L17 VDDCR_SOC L18 VDDCR_SOC L21 VDDCR_SOC L22 VDDCR_SOC L25 VDDCR_SOC L26 VDDCR_SOC L29 VDDCR_SOC L30 VDDCR_SOC L33 VDDCR_SOC L34 VDDCR_SOC L35 VD...

Page 166: ...5 VDDCR_SOC N26 VDDCR_SOC N29 VDDCR_SOC N30 VDDCR_SOC N45 VDDCR_SOC P13 VDDCR_SOC P14 VDDCR_SOC P17 VDDCR_SOC P18 VDDCR_SOC P21 VDDCR_SOC P22 VDDCR_SOC P25 VDDCR_SOC P26 VDDCR_SOC P29 VDDCR_SOC P30 VD...

Page 167: ...6 VDDCR_SOC T29 VDDCR_SOC T30 VDDCR_SOC T31 VDDCR_SOC T32 VDDCR_SOC T33 VDDCR_SOC T34 VDDCR_SOC T35 VDDCR_SOC T36 VDDCR_SOC T39 VDDCR_SOC T43 VDDCR_SOC T45 VDDCR_SOC U13 VDDCR_SOC U14 VDDCR_SOC U17 VD...

Page 168: ...1 VDDCR_SOC W32 VDDCR_SOC W33 VDDCR_SOC W34 VDDCR_SOC W35 VDDCR_SOC W36 VDDCR_SOC W37 VDDCR_SOC W41 VDDCR_SOC W45 VDDCR_SOC Y13 VDDCR_SOC Y14 VDDCR_SOC Y17 VDDCR_SOC Y18 VDDCR_SOC Y21 VDDCR_SOC Y22 VD...

Page 169: ...R_SOC AB45 VDDCR_SOC AC13 VDDCR_SOC AC14 VDDCR_SOC AC17 VDDCR_SOC AC18 VDDCR_SOC AC21 VDDCR_SOC AC22 VDDCR_SOC AC23 VDDCR_SOC AC24 VDDCR_SOC AC25 VDDCR_SOC AC26 VDDCR_SOC AC27 VDDCR_SOC AC28 VDDCR_SOC...

Page 170: ...DCR_SOC AD35 VDDCR_SOC AD36 VDDCR_SOC AD39 VDDCR_SOC AD43 VDDCR_SOC AD45 VDDCR_SOC AE13 VDDCR_SOC AE14 VDDCR_SOC AE17 VDDCR_SOC AE18 VDDCR_SOC AE45 VDDCR_SOC AF17 VDDCR_SOC AF18 VDDCR_SOC AF45 VDDCR_S...

Page 171: ...DCR_SOC AH24 VDDCR_SOC AH25 VDDCR_SOC AH26 VDDCR_SOC AH27 VDDCR_SOC AH28 VDDCR_SOC AH29 VDDCR_SOC AH30 VDDCR_SOC AH31 VDDCR_SOC AH32 VDDCR_SOC AH33 VDDCR_SOC AH34 VDDCR_SOC AH35 VDDCR_SOC AH36 VDDCR_S...

Page 172: ...DCR_SOC AU41 VDDIO_MEM AP16 VDDIO_MEM AP30 VDDIO_MEM AR19 VDDIO_MEM AR22 VDDIO_MEM AR25 VDDIO_MEM AR28 VDDIO_MEM AR31 VDDIO_MEM AT17 VDDIO_MEM AT18 VDDIO_MEM AT21 VDDIO_MEM AT24 VDDIO_MEM AT27 VDDIO_M...

Page 173: ...8 AG5 VDD_18 AH5 VDD_080 AL7 VDD_080 AM8 VDD_080 AP8 VDD_080 AT8 VDD_080 AV4 VDD_080 AV7 VDD_080 AV10 VDD_080 AW3 VDD_080 AW6 VDD_080 AW9 VDD_080_EFUSE AK8 VDD_080_EFUSE AK9 VPP BD26 VPP BE26 VPP BE27...

Page 174: ...E9 VSS E13 VSS E17 VSS E21 VSS E25 VSS E29 VSS E33 VSS E37 VSS E41 VSS F1 VSS F4 VSS F7 VSS F11 VSS F39 VSS F43 VSS G3 VSS G6 VSS G9 VSS G13 VSS G17 VSS G21 VSS G25 VSS G29 VSS G33 VSS G37 VSS G41 VS...

Page 175: ...9 VSS K20 VSS K23 VSS K24 VSS K27 VSS K28 VSS K31 VSS K32 VSS K35 VSS K36 VSS L3 VSS L5 VSS L9 VSS L12 VSS L15 VSS L16 VSS L19 VSS L20 VSS L23 VSS L24 VSS L27 VSS L28 VSS L31 VSS L32 VSS M1 VSS M4 VSS...

Page 176: ...2 VSS N15 VSS N16 VSS N19 VSS N20 VSS N23 VSS N24 VSS N27 VSS N28 VSS N31 VSS N32 VSS N33 VSS N34 VSS N35 VSS N36 VSS N37 VSS N41 VSS P1 VSS P4 VSS P7 VSS P11 VSS P12 VSS P15 VSS P16 VSS P19 VSS P20 V...

Page 177: ...R15 VSS R16 VSS R19 VSS R20 VSS R23 VSS R24 VSS R27 VSS R28 VSS T1 VSS T4 VSS T7 VSS T11 VSS T12 VSS T15 VSS T16 VSS T19 VSS T20 VSS T23 VSS T24 VSS T27 VSS T28 VSS U3 VSS U6 VSS U9 VSS U12 VSS U15 VS...

Page 178: ...U41 VSS V1 VSS V4 VSS V8 VSS V11 VSS V12 VSS V15 VSS V16 VSS V19 VSS V20 VSS V23 VSS V24 VSS V27 VSS V28 VSS V29 VSS V30 VSS V31 VSS V32 VSS V33 VSS V34 VSS V35 VSS V36 VSS V39 VSS V43 VSS W3 VSS W6...

Page 179: ...S Y24 VSS AA3 VSS AA6 VSS AA9 VSS AA12 VSS AA15 VSS AA16 VSS AA19 VSS AA20 VSS AA23 VSS AA24 VSS AA25 VSS AA26 VSS AA27 VSS AA28 VSS AA29 VSS AA30 VSS AA31 VSS AA32 VSS AA33 VSS AA34 VSS AA35 VSS AA36...

Page 180: ...SS AB30 VSS AB31 VSS AB32 VSS AB33 VSS AB34 VSS AB35 VSS AB36 VSS AB39 VSS AB43 VSS AC3 VSS AC5 VSS AC9 VSS AC12 VSS AC15 VSS AC16 VSS AC19 VSS AC20 VSS AD1 VSS AD4 VSS AD7 VSS AD11 VSS AD12 VSS AD15...

Page 181: ...AE29 VSS AE30 VSS AE31 VSS AE32 VSS AE33 VSS AE34 VSS AE35 VSS AE36 VSS AE37 VSS AE41 VSS AF1 VSS AF4 VSS AF7 VSS AF11 VSS AF12 VSS AF13 VSS AF14 VSS AF15 VSS AF16 VSS AF19 VSS AF20 VSS AF21 VSS AF22...

Page 182: ...SS AG14 VSS AG15 VSS AG16 VSS AH1 VSS AH4 VSS AH7 VSS AH8 VSS AH11 VSS AH12 VSS AH13 VSS AH14 VSS AH15 VSS AH16 VSS AJ3 VSS AJ6 VSS AJ9 VSS AJ12 VSS AJ13 VSS AJ19 VSS AJ22 VSS AJ25 VSS AJ28 VSS AJ31 V...

Page 183: ...SS AL1 VSS AL3 VSS AL9 VSS AL12 VSS AL13 VSS AL16 VSS AM2 VSS AM4 VSS AM7 VSS AM11 VSS AM12 VSS AM13 VSS AM16 VSS AN7 VSS AN9 VSS AN13 VSS AN16 VSS AN18 VSS AN21 VSS AN24 VSS AN27 VSS AN30 VSS AN33 VS...

Page 184: ...AT3 VSS AT7 VSS AT11 VSS AT13 VSS AT15 VSS AT38 VSS AU10 VSS AU12 VSS AU13 VSS AU17 VSS AU20 VSS AU23 VSS AU26 VSS AU29 VSS AU32 VSS AU35 VSS AU45 VSS AV5 VSS AV6 VSS AV9 VSS AV11 VSS AV25 VSS AV28 V...

Page 185: ...AY10 VSS AY13 VSS AY16 VSS AY19 VSS AY22 VSS AY39 VSS AY43 VSS BA5 VSS BA6 VSS BA9 VSS BA12 VSS BA15 VSS BA18 VSS BA21 VSS BA22 VSS BA27 VSS BA31 VSS BA34 VSS BA37 VSS BA41 VSS BB4 VSS BB5 VSS BB8 VSS...

Page 186: ...S BC30 VSS BC32 VSS BC35 VSS BC38 VSS BC41 VSS BC44 VSS BC45 VSS BD1 VSS BD5 VSS BD6 VSS BD9 VSS BD12 VSS BD15 VSS BD18 VSS BD21 VSS BD23 VSS BD25 VSS BD34 VSS BD37 VSS BD40 VSS BD43 VSS BD44 VSS BD45...

Page 187: ...SS BE21 VSS BE25 VSS BE28 VSS BE34 VSS BE37 VSS BE39 VSS BE42 VSS BE43 VSS BE44 WAKEB BD2 XTALIN AM1 XTALOUT AM3 XTRIG6 AD9 XTRIG7 AG9 Pin Listings 175 2017 Advanced Micro Devices Inc AMD Confidential...

Page 188: ...176 Pin Listings Vega 10 Databook 56006_1 00 2017 Advanced Micro Devices Inc AMD Confidential Do not duplicate...

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