Rail Name
Nominal
Voltage
DC Tolerance
AC Tolerance
Maximum
Current
Notes
VDD_18
VDDAN_18
VDDAN_Q_EFUSE
1.8 V
±3%
±3%
3.5 A (TDC)
5, 6, 7
VDDAN_33
3.3 V
±3%
±3%
0.1 A (TDC)
VPP
2.5 V
±3%
±3%
1.5 A (TDC)
Note:
1.
Use the main domain of SVI2 regulator. The SVI2 regulator can provide any voltage required on
VDDCR_SOC. Voltage quoted corresponds to the VID code sent from GPU to the voltage regulator
in the SVD data package.
2.
Sufficient EDC capacity should be allocated to the VDDCR_SOC rail in order for the GPU to burst
into higher performance levels opportunistically without violating the given thermal constraints
(TDC/TGP).
3.
The two rails can be merged on the PCB and supplied by the second domain of the SVI2 regulator.
Contact AMD for guidance on how to set the second domain of the SVI2 regulator to meet HBM
power up requirements.
4.
AMD requires the use of load line on the VDDCR_SOC rail. The load line value is 0.25 mΩ.
5.
If a switching regulator is used to power the 1.8-V rails, a filter inductor should be placed between
the output of the regulator circuit and the GPU decoupling capacitors, and outside the feedback loop
of the switching regulator. The filter inductor should be of 0.24 µH, and its DCR should be of 15
mΩ or less. The LDO solution does not need the filter inductor.
6.
For the switching regulator, tolerance is defined at the 1.8-V regulator output before the filter
inductor.
7.
The three rails can be merged on the PCB and supplied by the same regulator.
8.
The three rails can be supplied by the same regulator. VDDCR_BACO should be isolated from the
other two rails by a bead.
9.
The quoted EDC value corresponds to the unconstrained GPU peak demand projected to cover the
entire GPU population at the maximum allowed GPU die temperature and operating frequencies
using a power virus-like, AMD proprietary utility that induces the heaviest transient load to GPU.
10.
AMD's Peak Current Control (PCC) technology can mitigate and contain the peak demand from GPU
thus reduce the EDC requirement if the required circuit is implemented on the board/platform.
5.2.1 Transient Behavior
The voltage regulator supplying VDDCR_SOC rail must exhibit equal or better
transient behavior with regard to the parameters (overshoot, undershoot and settling
time) listed in the following tables.
Electrical Characteristics
59
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2017
Advanced Micro Devices, Inc.
AMD Confidential - Do not duplicate.
"Vega 10" Databook
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