Pin Name
Type
Description
GENERICD_HPD3
GENERICE_HPD4
GENERICF_HPD5
GENERICG_HPD6
3.14 Test/JTAG Interface
In order to debug issues, AMD requires access to the JTAG and debug ports unless
specified otherwise.
Test points can be used on the JTAG signals to minimize the PCB space needed.
Note: The JTAG interface on "Vega 10" is 1.8 V.
Table 3–15 Test/JTAG Interface
Pin Name
Type
Description
TESTEN
I
1.8 V
(VDDAN_18)
Reserved signal.
This pin must be tied to ground through a 1-kΩ to 10-kΩ resistor for normal
GPU operation.
TRST_L
I
1.8 V
(VDDAN_18)
TRSTB (test reset).
This pin can be left floating, or tied to 1.8 V through a 10-kΩ resistor for normal
GPU operation.
Must be accessible on all PCBs through a test point or resistor pad.
TDI
I
1.8 V
(VDDAN_18)
TDI (test data input).
This pin can be left floating, or tied to 1.8 V through a 10-kΩ resistor for normal
GPU operation.
Must be accessible on all PCBs through a test point or resistor pad.
TCK
I
1.8 V
(VDDAN_18)
TCK (test clock).
This pin can be left floating, or tied to ground through a 10-kΩ resistor for
normal GPU operation.
Must be accessible on all PCBs through a test point or resistor pad.
TMS
I
1.8 V
(VDDAN_18)
TMS (test mode select).
This pin can be left floating, or tied to 1.8 V through a 10-kΩ resistor for normal
GPU operation.
Must be accessible on all PCBs through a test point or resistor pad.
TDO
O
1.8 V
(VDDAN_18)
TDO (test data output).
This pin can be left floating, or unconnected if not used.
Must be accessible on all PCBs through a test point or resistor pad.
DBREQ_L
I
1.8 V
(VDDAN_18)
Additional debug input.
This pin must have a 1 kΩ pullup to 1.8 V and a 0.01 µF filter capacitor to
ground.
32
Signal Descriptions
"Vega 10" Databook
56006_1.00
©
2017
Advanced Micro Devices, Inc.
AMD Confidential - Do not duplicate.
