AMD Vega 10, Data Book

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2
Functional Overview
This section describes the major subsystems and interfaces of "Vega 10". To go to a
topic of interest, use the following list of linked cross-references:
• Memory Interface (p. 3)
• Acceleration Features (p. 5)
• Display System (p. 6)
• Video Acceleration Features (p. 13)
• Video Codec Engine (VCE) Features (p. 14)
• PCI Express® Bus Support Features (p. 15)
• Power Management Features (p. 15)
• Spread-spectrum Support (p. 16)
• Internal Thermal Sensor (p. 16)
• Thermal Diode (p. 16)
• Logo Compliance (p. 17)
• Test Capability Features (p. 17)
• Other Features (p. 17)
• Export Control Classification (p. 18)
2.1 Memory Interface
2.1.1 Memory Configurations Support
"Vega 10" adopts second generation HBM (high-bandwidth memory) technology with
two HBM memory stacks embedded together with the GPU die through a silicon
interposer. Therefore "Vega 10" designs do not need nor do they support external
video memory.
Each memory stack has 16 pseudo channels of 64-bit width each. Therefore, the total
interface between the GPU and memory is 2048-bits wide.
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"Vega 10" Databook
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