AMD Athlon™ Processor Microarchitecture
133
22007E/0—November 1999
AMD Athlon™ Processor x86 Code Optimization
return stack. Subsequent RETs pop a predicted return address
off the top of the stack.
Early Decoding
T h e D i r e c t Pa t h a n d Ve c t o r Pa t h d e c o d e r s p e r f o r m
early-decoding of instructions into MacroOPs. A MacroOP is a
fixed length instruction which contains one or more OPs. The
o u t p u t s o f t h e e a rly d e c o d e rs ke e p a l l ( D ire c t Pa t h o r
VectorPath) instructions in program order. Early decoding
produces three MacroOPs per cycle from either path. The
outputs of both decoders are multiplexed together and passed
to the next stage in the pipeline, the instruction control unit.
When the target 16-byte instruction window is obtained from
the instruction cache, the predecode data is examined to
deter m in e whi ch t y p e of bas ic decod e sh oul d occ ur —
DirectPath or VectorPath.
DirectPath Decoder
DirectPath instructions can be decoded directly into a
MacroOP, and subsequently into one or two OPs in the final
issue stage. A DirectPath instruction is limited to those x86
instructions that can be further decoded into one or two OPs.
The length of the x86 instruction does not determine DirectPath
instructions. A maximum of three DirectPath x86 instructions
can occupy a given aligned 8-byte block. 16-bytes are fetched at
a time. Therefore, up to six DirectPath x86 instructions can be
passed into the DirectPath decode pipeline.
VectorPath Decoder
Uncommon x86 instructions requiring two or more MacroOPs
proceed down the VectorPath pipeline. The sequence of
MacroOPs is produced by an on-chip ROM known as the MROM.
The VectorPath decoder can produce up to three MacroOPs per
cycle. Decoding a VectorPath instruction may prevent the
simultaneous decode of a DirectPath instruction.
Summary of Contents for Athlon Processor x86
Page 1: ...AMD Athlon Processor x86 Code Optimization Guide TM...
Page 12: ...xii List of Figures AMD Athlon Processor x86 Code Optimization 22007E 0 November 1999...
Page 16: ...xvi Revision History AMD Athlon Processor x86 Code Optimization 22007E 0 November 1999...
Page 202: ...186 Page Attribute Table PAT AMD Athlon Processor x86 Code Optimization 22007E 0 November 1999...
Page 252: ...236 VectorPath Instructions AMD Athlon Processor x86 Code Optimization 22007E 0 November 1999...
Page 256: ...240 Index AMD Athlon Processor x86 Code Optimization 22007E 0 November 1999...