AMD Athlon Processor x86, Optimization Manual, Page: 190 / 256

174 Memory Type Range Register (MTRR) Mechanism
AMD Athlon™ Processor x86 Code Optimization
22007E/0—November 1999
Memory Types
Five standard memory types are defined by the AMD Athlon
processor: writethrough (WT), writeback (WB), write-protect
(WP), write-combining (WC), and uncacheable (UC). These are
described in Table 12 on page 174.
MTRR Capability
Register Format The MTRR capability register is a read-only register that
defines the specific MTRR capability of the processor and is
defined as follows.
Figure 13. MTRR Capability Register Format
For the AMD Athlon processor, the MTRR capability register
s h o u l d c on t a in 0 5 0 8 h ( w r i t e - c o m b in i n g , f ix e d MT R R s
supported, and eight variable MTRRs defined).
Table 12. Memory Type Encodings
Type Number Type Name Type Description
00h UC—Uncacheable
Uncacheable for reads or writes. Cannot be combined. Must be
non-speculative for reads or writes.
01h WC—Write-Combining
Uncacheable for reads or writes. Can be combined. Can be speculative for
reads. Writes can never be speculative.
04h WT—Writethrough
Reads allocate on a miss, but only to the S-state. Writes do not allocate on
a miss and, for a hit, writes update the cached entry and main memory.
05h WP—Write-Protect
WP is functionally the same as the WT memory type, except stores do not
actually modify cached data and do not cause an exception.
06h WB—Writeback
Reads will allocate on a miss, and will allocate to:
S state if returned with a ReadDataShared command.
M state if returned with a ReadDataDirty command.
Writes allocate to the M state, if the read allows the line to be marked E.
8 7 0
63
F
I
X
9 10 11
W
C
VCNT
Symbol Description Bits
WC Write Combining Memory Type 10
FIX Fixed Range Registers 8
VCNT No. of Variable Range Registers 7–0
Reserved