AMD Athlon Processor x86, Optimization Manual, Page: 178 / 256

162 Performance Counter Usage
AMD Athlon™ Processor x86 Code Optimization
22007E/0—November 1999
These registers can be read from and written to using the
RDMSR and WRMSR instructions, respectively.
The PerfEvtSel[3:0] registers are located at MSR locations
C001_0000h to C001_0003h. The PerfCtr[3:0] registers are
located at MSR locations C001_0004h to C0001_0007h and are
64-byte registers.
The PerfEvtSel[3:0] registers can be accessed using the
RDMSR/WRMSR instructions only when operating at privilege
level 0. The PerfCtr[3:0] MSRs can be read from any privilege
level using the RD PMC (re ad performa nce -monito ring
counters) instruction, if the PCE flag in CR4 is set.
PerfEvtSel[3:0] MSRs (MSR Addresses C001_0000h–C001_0003h)
The PerfEvtSel[3:0] MSRs, shown in Figure 11, control the
operation of the performance-monitoring counters, with one
register used to set up each counter. These MSRs specify the
events to be counted, how they should be counted, and the
privilege levels at which counting should take place. The
functions of the flags and fields within these MSRs are as are
described in the following sections.
Figure 11. PerfEvtSel[3:0] Registers
Event Select Field
(Bits 0—7)
These bits are used to select the event to be monitored. See
Table 11 on page 164 for a list of event masks and their 8-bit
codes.
9 8 7 6 5 4 3 2 1 0 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22
O
S
I
N
T
U
S
R
Reserved
P
C E E
N
I
N
V
Unit Mask Event Mask
Counter Mask
Symbol Description Bit
USR User Mode 16
OS Operating System Mode 17
E Edge Detect 18
PC Pin Control 19
INT APIC Interrupt Enable 20
EN Enable Counter 22
INV Invert Mask 23