AMD Athlon Processor x86, Optimization Manual, Page: 165 / 256

Execution Unit Resources 149
22007E/0—November 1999
AMD Athlon™ Processor x86 Code Optimization
Integer Pipeline Operations
Table 2 shows the category or type of operations handled by the
integer pipeline. Table 3 shows examples of the decode type.
As shown in Table 2, the MOV instruction early decodes in the
DirectPath decoder and requires two OPs—an address
generation operation for the indirect address and a data load
from memory into a register. The ADD instruction early
decodes in the DirectPath decoder and requires a single OP
that can be executed in one of the three IEUs. The CMP
instruction early decodes in the VectorPath and requires three
OPs—an address generation operation for the indirect address,
a data load from memory, and a compare to CX using an IEU.
The final JZ instruction is a simple operation that early decodes
in the DirectPath decoder and requires a single OP. Not shown
is a load-op-store instruction, which translates into only one
MacroOP (one AGU OP, one IEU OP, and one L/S OP).
Table 2. Integer Pipeline Operation Types
Category Execution Unit
Integer Memory Load or Store Operations L/S
Address Generation Operations AGU
Integer Execution Unit Operations IEU
Integer Multiply Operations IMUL
Table 3. Integer Decode Types
x86 Instruction Decode Type OPs
MOV CX, [SP+4] DirectPath AGU, L/S
ADD AX, BX DirectPath IEU
CMP CX, [AX] VectorPath AGU, L/S, IEU
JZ Addr DirectPath IEU