22007E/0—November 1999
AMD Athlon™ Processor x86 Code Optimization
Fetch and Decode Pipeline Stages
141
Appendix B
Pipeline and Execution Unit
Resources Overview
The AMD Athlon™ processor contains two independent
execution pipelines — one for integer operations and one for
floating-point operations. The integer pipeline manages x86
integer operations and the floating-point pipeline manages all
x87, 3DNow!™ and MMX™ instructions. This appendix
describes the operation and functionality of these pipelines.
Fetch and Decode Pipeline Stages
Figure 5 on page 142 and Figure 6 on page 142 show the
AMD Athlon processor instruction fetch and decoding pipeline
stages. The pipeline consists of one cycle for instruction fetches
and four cycles of instruction alignment and decoding. The
three ports in stage 5 provide a maximum bandwidth of three
MacroOPs per cycle for dispatching to the instruction control
unit (ICU).
Summary of Contents for Athlon Processor x86
Page 1: ...AMD Athlon Processor x86 Code Optimization Guide TM...
Page 12: ...xii List of Figures AMD Athlon Processor x86 Code Optimization 22007E 0 November 1999...
Page 16: ...xvi Revision History AMD Athlon Processor x86 Code Optimization 22007E 0 November 1999...
Page 202: ...186 Page Attribute Table PAT AMD Athlon Processor x86 Code Optimization 22007E 0 November 1999...
Page 252: ...236 VectorPath Instructions AMD Athlon Processor x86 Code Optimization 22007E 0 November 1999...
Page 256: ...240 Index AMD Athlon Processor x86 Code Optimization 22007E 0 November 1999...