Page Attribute Table (PAT)
181
22007E/0—November 1999
AMD Athlon™ Processor x86 Code Optimization
●
●
CD
-
●
●
CD
●
●
WC
-
●
●
WC
●
●
WT
-
●
●
WT
●
●
WP
-
●
●
WP
●
●
WB
-
●
●
WT
4
●
●
-
●
●
●
CD
2
Notes:
1. WP is not functional for RdMem/WrMem.
2. ForceCD must cause the MTRR memory type to be ignored in order to avoid x’s.
3. D-I should always be WP because the BIOS will only program RdMem-WrIO for WP. CD
is forced to preserve the write-protect intent.
4. Since cached IO lines cannot be copied back to IO, the processor forces WB to WT to
prevent cached IO from going dirty.
5. ForceCD. The memory type is forced CD due to (1) CR0[CD]=1, (2) memory type is for
the ITLB and the I-Cache is disabled or for the DTLB and the D-Cache is disabled, (3)
when clean victims must be written back and RdIO and WrIO and WT, WB, or WP, or
(4) access to Local APIC space.
6. The processor does not support this memory type.
Table 16. Final Output Memory Types (Continued)
Input Memory Type
Output Memory Type
Note
Rd
M
em
Wr
M
em
Effe
ct
iv
e. M
Type
for
ce
C
D
5
AMD-751
RdM
em
Wr
M
em
Me
m
Ty
p
e
Summary of Contents for Athlon Processor x86
Page 1: ...AMD Athlon Processor x86 Code Optimization Guide TM...
Page 12: ...xii List of Figures AMD Athlon Processor x86 Code Optimization 22007E 0 November 1999...
Page 16: ...xvi Revision History AMD Athlon Processor x86 Code Optimization 22007E 0 November 1999...
Page 202: ...186 Page Attribute Table PAT AMD Athlon Processor x86 Code Optimization 22007E 0 November 1999...
Page 252: ...236 VectorPath Instructions AMD Athlon Processor x86 Code Optimization 22007E 0 November 1999...
Page 256: ...240 Index AMD Athlon Processor x86 Code Optimization 22007E 0 November 1999...