AMD Athlon Processor x86, Optimization Manual, Page: 160 / 256

144 Integer Pipeline Stages
AMD Athlon™ Processor x86 Code Optimization
22007E/0—November 1999
operands mapped to registers. Both integer and floating-point
MacroOPs are placed into the ICU.
Integer Pipeline Stages
The integer execution pipeline consists of four or more stages
for scheduling and execution and, if necessary, accessing data
in the processor caches or system memory. There are three
integer pipes associated with the three IEUs.
Figure 7. Integer Execution Pipeline
Figure 7 and Figure 8 show the integer execution resources and
the pipeline stages, which are described in the following
sections.
Figure 8. Integer Pipeline Stages
IEU1
IEU1
Instruction Control Unit and Register Files
Integer Multiply (IM UL)
Integer M ultiply (IM UL)
IEU 0
IEU0
AGU0
AGU0
AGU1
AGU 1
IEU2
IEU2
AGU2
AGU2
M acroOPs M acroOPs
Pipeline
Pipeline
Stage
Stage
Integer Scheduler
(18-entry)
7 7
8
8
S C H E D E X E C A D D G E N
7
8
9
D C A C C
1 0
R E S P
11