Instruction Dispatch and Execution Resources
209
22007E/0—November 1999
AMD Athlon™ Processor x86 Code Optimization
PANDN mmreg1, mmreg2
0Fh
DFh
11-xxx-xxx
DirectPath
FADD/FMUL
PANDN mmreg, mem64
0Fh
DFh
mm-xxx-xxx
DirectPath
FADD/FMUL
PCMPEQB mmreg1, mmreg2
0Fh
74h
11-xxx-xxx
DirectPath
FADD/FMUL
PCMPEQB mmreg, mem64
0Fh
74h
mm-xxx-xxx
DirectPath
FADD/FMUL
PCMPEQD mmreg1, mmreg2
0Fh
76h
11-xxx-xxx
DirectPath
FADD/FMUL
PCMPEQD mmreg, mem64
0Fh
76h
mm-xxx-xxx
DirectPath
FADD/FMUL
PCMPEQW mmreg1, mmreg2
0Fh
75h
11-xxx-xxx
DirectPath
FADD/FMUL
PCMPEQW mmreg, mem64
0Fh
75h
mm-xxx-xxx
DirectPath
FADD/FMUL
PCMPGTB mmreg1, mmreg2
0Fh
64h
11-xxx-xxx
DirectPath
FADD/FMUL
PCMPGTB mmreg, mem64
0Fh
64h
mm-xxx-xxx
DirectPath
FADD/FMUL
PCMPGTD mmreg1, mmreg2
0Fh
66h
11-xxx-xxx
DirectPath
FADD/FMUL
PCMPGTD mmreg, mem64
0Fh
66h
mm-xxx-xxx
DirectPath
FADD/FMUL
PCMPGTW mmreg1, mmreg2
0Fh
65h
11-xxx-xxx
DirectPath
FADD/FMUL
PCMPGTW mmreg, mem64
0Fh
65h
mm-xxx-xxx
DirectPath
FADD/FMUL
PMADDWD mmreg1, mmreg2
0Fh
F5h
11-xxx-xxx
DirectPath
FMUL
PMADDWD mmreg, mem64
0Fh
F5h
mm-xxx-xxx
DirectPath
FMUL
PMULHW mmreg1, mmreg2
0Fh
E5h
11-xxx-xxx
DirectPath
FMUL
PMULHW mmreg, mem64
0Fh
E5h
mm-xxx-xxx
DirectPath
FMUL
PMULLW mmreg1, mmreg2
0Fh
D5h
11-xxx-xxx
DirectPath
FMUL
PMULLW mmreg, mem64
0Fh
D5h
mm-xxx-xxx
DirectPath
FMUL
POR mmreg1, mmreg2
0Fh
EBh
11-xxx-xxx
DirectPath
FADD/FMUL
POR mmreg, mem64
0Fh
EBh
mm-xxx-xxx
DirectPath
FADD/FMUL
PSLLD mmreg1, mmreg2
0Fh
F2h
11-xxx-xxx
DirectPath
FADD/FMUL
PSLLD mmreg, mem64
0Fh
F2h
mm-xxx-xxx
DirectPath
FADD/FMUL
PSLLD mmreg, imm8
0Fh
72h
11-110-xxx
DirectPath
FADD/FMUL
PSLLQ mmreg1, mmreg2
0Fh
F3h
11-xxx-xxx
DirectPath
FADD/FMUL
PSLLQ mmreg, mem64
0Fh
F3h
mm-xxx-xxx
DirectPath
FADD/FMUL
PSLLQ mmreg, imm8
0Fh
73h
11-110-xxx
DirectPath
FADD/FMUL
PSLLW mmreg1, mmreg2
0Fh
F1h
11-xxx-xxx
DirectPath
FADD/FMUL
PSLLW mmreg, mem64
0Fh
F1h
mm-xxx-xxx
DirectPath
FADD/FMUL
PSLLW mmreg, imm8
0Fh
71h
11-110-xxx
DirectPath
FADD/FMUL
Table 20. MMX™ Instructions (Continued)
Instruction Mnemonic
Prefix
Byte(s)
First
Byte
ModR/M
Byte
Decode
Type
FPU Pipe(s)
Notes
Notes:
1. Bits 2, 1, and 0 of the modR/M byte select the integer register.
Summary of Contents for Athlon Processor x86
Page 1: ...AMD Athlon Processor x86 Code Optimization Guide TM...
Page 12: ...xii List of Figures AMD Athlon Processor x86 Code Optimization 22007E 0 November 1999...
Page 16: ...xvi Revision History AMD Athlon Processor x86 Code Optimization 22007E 0 November 1999...
Page 202: ...186 Page Attribute Table PAT AMD Athlon Processor x86 Code Optimization 22007E 0 November 1999...
Page 252: ...236 VectorPath Instructions AMD Athlon Processor x86 Code Optimization 22007E 0 November 1999...
Page 256: ...240 Index AMD Athlon Processor x86 Code Optimization 22007E 0 November 1999...