Chapter 2: Getting Started with the Stratix V Hard IP for PCI Express
2–9
MegaWizard Plug-In Manager Design Flow
June 2012
Altera Corporation
Stratix V Hard IP for PCI Express
Figure 2–4
illustrates the GUI for the APPS component. In
Figure 2–4
the block
diagram shows interfaces. If you click
Show signals
, the block diagram expands
to show all of the signals in the APPS component.
1
You can use this Qsys APPS component to test any Endpoint variant with
the compatible values for these parameters.
5. To close the
APPS
component, click the
X
in the upper right-hand corner of the
parameter editor.
6. On the Qsys
Generation
tab, specify the parameters listed in
Table 2–15
.
Figure 2–4. Qsys Component Representing the Chaining DMA Design
Table 2–7. Parameters to Specify on the Generation Tab in Qsys (Part 1 of 2)
Parameter
Value
Simulation
Create simulation model
Verilog -
This option creates a simulation model that you can include in your own custom
testbench.
Create testbench Qsys system Standard, BFMs for standard Avalon interfaces
Create testbench simulation
model
Verilog
Synthesis
Create HDL design files for
synthesis
Turn this option on
Create block symbol file (.bsf)
Turn this option on