6–50
Chapter 6: IP Core Interfaces
Avalon-MM Interface
Stratix V Hard IP for PCI Express
June 2012
Altera Corporation
RX Avalon-MM Master Signals
This Avalon-MM master port propagates PCI Express requests to the Qsys
interconnect fabric. For the full-feature IP core it propagates requests as bursting reads
or writes. A separate Avalon-MM master port corresponds to each BAR. Signals that
include lane number 0 also exist for BAR1–BAR5 when additional BARs are enabled.
Table 6–26
lists the RX Master interface ports.
cra_write
I
Write
Write request
cra_writedata[31:0]
I
Writedata
Write data
Table 6–25. Avalon-MM CRA Slave Interface Signals (Part 2 of 2)
Signal Name
I/O
Type
Description
Table 6–26. Avalon-MM RX Master Interface Signals
Signal Name
I/O
Description
rxm_bar0_write_<n>
O
Asserted by the core to request a write to an Avalon-MM slave.
rxm_bar0_address_<n>[31:0]
O
The address of the Avalon-MM slave being accessed.
rxm_bar0_writedata_<n>[<w>-1:0]
O
RX data being written to slave.
<w>
= 64 for the full-featured IP core.
<w>
= 32 for the completer-only IP core.
rxm_bar0_byteenable_<n>
[<w>-1:0]
O
Byte enable for write data.
rxm_bar0_burstcount_<n>[6:0]
O
The burst count, measured in qwords, of the RX write or read request. The
width indicates the maximum data that can be requested. The maximum
data in a burst is 512 bytes.
rxm_bar0_waitrequest_<n>
I
Asserted by the external Avalon-MM slave to hold data transfer.
rxm_bar0_read_<n>
O
Asserted by the core to request a read.
rxm_bar0_readdata_<n>[<w>-1:0]
I
Read data returned from Avalon-MM slave in response to a read request.
This data is sent to the IP core through the TX interface.
<w>
= 64 for the
full-featured IP core.
<w>
= 32 for the completer-only IP core.
rxm_bar0_readdatavalid_<n>
I
Asserted by the system interconnect fabric to indicate that the read data on
is valid.
rxm_irq_<n>[<m>:0]
I
Indicates an interrupt request asserted from the system interconnect fabric.
This signal is only available when the CRA port is enabled. Qsys-generated
variations have as many as 16 individual interrupt signals (
<m>
≤
15).
Note to
Table 6–26
:
(1) <n> represents the BAR number for all signals. The core supports up to 6 BARs.