6–62
Chapter 6: IP Core Interfaces
Test Signals
Stratix V Hard IP for PCI Express
June 2012
Altera Corporation
Test Signals
The
test_in
and
test_out
buses provide run-time control and monitoring of the
internal state of the Stratix V Hard IP for PCI Express.
describes the test
signals.
c
Altera recommends that you use the
test_out
and
test_in
signals for debug or
non-critical status monitoring purposes such as LED displays of PCIe link status.
They should not be used for design function purposes. Use of these signals will make
it more difficult to close timing on the design. The test signals have not been
rigorously verified and will not function as documented in some corner cases. The
debug signals provided on
test_out
are not available in the current release.
ltssmstate0[4:0]
(continued)
O
■
5’b10000: Disable
■
5’b10001: Loopback.Entry
■
5’b10010: Loopback.Active
■
5’b10011: Loopback.Exit
■
5’b10100: Hot.Reset
■
5’b10101: LOs
■
5’b11001: L2.transmit.Wake
■
5’b11010: Speed.Recovery
■
5’b11011: Recovery.Equalization, Phase 0
■
5’b11100: Recovery.Equalization, Phase 1
■
5’b11101: Recovery.Equalization, Phase 2
■
5’b11110: recovery.Equalization, Phase 3
rate[1:0]
O
The 2-bit encodings have the following meanings:
■
2’b00: Gen1 rate (2.5 Gbps)
■
2’b01: Gen2 rate (5.0 Gbps)
■
2’b1X: Gen3 rate (8.0 Gbps)
pclk_in
I
This clock is used for PIPE simulation only, and is derived from the
refclk
. It is the PIPE interface clock used for PIPE mode simulation.
tx_margin[2:0]
O
Transmit V
OD
margin selection. The value for this signal is based on the
value from the
Link Control 2
Register
. Available for simulation
only.
txswing
O
When asserted, indicates full swing for the transmitter voltage. When
deasserted indicates half swing.
testin_zero
O
When asserted, indicates accelerated initialization for simulation is
active.
Notes to
(1) Signals that include lane number 0 also exist for lanes 1-7.
(2) These signals are for simulation only. For Quartus II software compilation, these pipe signals can be left floating.
Table 6–31. PIPE Interface Signals (Part 3 of 3)
Signal I/O
Description