Page 42
Example Project Walkthrough
AN 436: Using DDR3 SDRAM in Stratix III and Stratix IV Devices
© November 2008
Altera Corporation
Virtual Pins
The example top-level design, which is autogenerated by the high- performance
controller, includes an example driver to stimulate the interface. This example driver
is not part of the SDRAM high-performance controller IP, but allows easy testing of
the IP.
The example driver outputs several test signals to indicate its operation and the status
of the stimulated memory interface. These signals are
pnf
,
pnf_per_byte
, and
test_complete
. These signals are not part of the memory interface, but are for
testing. You should take these signals to either a debug header or set the signals to
virtual pin using the Quartus II Assignment Editor. When using the example driver
for testing, do not remove these signals from the top-level signal list. Otherwise the
Quartus II software optimizes the driver away, and the example driver fails.
To assign virtual pin assignments for the Stratix III memory demonstration board, run
the Altera-provided
s3_MB1_ddr3_exdriver_vpin.tcl
file or manually assign virtual
pin assignments using the Assignment Editor.
1
The memory interface pins (
DQ
,
DQS
,
DM
,
CK
,
CK#
, address and command) cannot be
assigned as virtual pins.
Advanced I/O Timing
ALTMEMPHY-based designs assume that the memory address and command signals
are matched length to the memory clock signals. Typically, this length match is not
true for DIMM-based designs. You should verify the difference in your design.
To amend the TimeQuest
.sdc
file, <
variation name
>
_phy_ddr_timing.sdc
, to include
this difference, follow these steps:
1. Open the
ddr3_dimm_phy_ddr_timing.sdc
file in a text editor and find the
following line (usually line 31):
set t(additional_addresscmd_tpd) 0.000
2. Change the line to the following text:
set t(additional_addresscmd_tpd) 0.300
3. Save the file.
1
If the DDR3 SDRAM controller
.sdc
file is regenerated, this change is lost
and you must re-edit the file.
Board Trace Delay Models
For accurate I/O timing analysis, the Quartus II must be aware of the board trace and
loading information. This information should be derived and refined during your
PCB development process of prelayout (line) simulation and finally post-layout
(board) simulation. For external memory interfaces that use memory modules
(DIMMs), this information should include the trace and loading information of the
module in addition to the main and host platform, which you can obtain from your
memory vendor.
To enter board trace information, follow these steps:
1. In
Pin Planner
, select the pin or group of pins that you want to enter the
information for.