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DDR3 SDRAM in Stratix III Devices Design Flow
AN 436: Using DDR3 SDRAM in Stratix III and Stratix IV Devices
© November 2008
Altera Corporation
f
For information about the FPGA density and package support for the different
memory types, refer to the
External Memory Interfaces in Stratix III Devices
chapter of
the
Stratix III Device Handbook
.
Full or Half Rate SDRAM Controller
When implementing memory controllers consider whether a half-rate or a full-rate
datapath is optimal for your design. Full or half-rate mode have the following
definitions:
■
Full-rate mode presents data to the local interface at twice the width of the actual
SDRAM interface at the full SDRAM clock rate
■
Half-rate mode presents data to the local interface at four times the width of the
actual SDRAM interface at half the SDRAM clock rate
Implementing memory controllers in half-rate mode results in the highest possible
SDRAM clock frequency, while allowing the more complex core logic to operate at
half this frequency. This implementation is most useful when core HDL designs are
difficult to implement at the higher SDRAM clock frequency, but the required
SDRAM bandwidth per I/O pin is still quite high.
1
DDR3 SDRAM minimum operating frequency is 300 MHz. The ALTMEMPHY
megafunction cannot achieve this frequency in full-rate implementations in Stratix III
devices.
PLL and Clock Usage
The exact number of clocks and hence PLLs required in your design depends greatly
on the memory interface frequency, and the IP used.
1
Stratix III IOE includes dedicated circuitry for postamble protection, which is derived
directly from the resynchronization clock.
In addition, some memory controller designs, like the ALTMEMPHY megafunction,
use a VT tracking clock to measure and compensate for VT changes and their effects.
Consider the following points:
■
PLLs in Stratix III devices connect to four maximum global clock nets
■
Top or bottom PLLs in Stratix III devices connect to ten maximum regional clock
nets
■
Left or right PLLs in Stratix III devices connect to six maximum regional clock nets
■
EP3S...80 and larger devices have two PLLs located in the middle of each side of
the device
■
EP3S...200 and larger device additionally have corner PLLs, which connect to six
regional clock nets only
■
Dual regional clock nets are created by using a regional clock net from each region.
For example, a single dual regional clock net uses two regional clock nets
■
If the design uses a dedicated PLL to only generate a DLL input reference clock,
the PLL mode must be set to
No Compensation
, or the Quartus II software forces
this setting automatically