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Altera Stratix III Using Manual Download Page 4

Page 4

Background

AN 436: Using DDR3 SDRAM in Stratix III and Stratix IV Devices

© November 2008

Altera Corporation

Table 2

 compares DDR, DDR2, and DDR3 SDRAM features.

IOE Dedicated DDR3 SDRAM Features 

Stratix III devices have enhanced upon the IOE DDR capabilities of previous 
generations of devices by including the following functionality availability directly in 
the IOE.

■

DDR registers

■

Alignment and synchronization registers (including I/O clock divider)

■

Half data-rate registers

■

DQS phase-shift circuitry (up to four DLLs each with two-phase offsets)

■

DQS postamble circuitry

Table 2.

DDR and DDR2 SDRAM Features

Feature

DDR SDRAM

DDR2 SDRAM

DDR3 SDRAM

DDR3 SDRAM Advantage

Voltage

2.5 V

1.8 V

1.5 V

Reduces memory system 
power demand by 17%.

Density

64 MB to 1GB

256 MB to 4 GB

512 MB to 8 GB

High-density components 
simplify memory 
subsystem.

Internal banks

4

4 and 8

8

Page-to-hit ratio increased.

Prefetch

2

4

8

Lower memory core speed 
results in higher operating 
frequency and lower power 
operation.

Speed

100 to 200 MHz

200 to 533 MHz

300 to 800 MHz

Higher data rate.

Read latency

2, 2.5, 3 clocks

3, 4, 5 clocks

5, 6, 7, 8, 9, 10, and 

11

Eliminating half clock 
setting allows 8n prefetch 
architecture.

Additive latency 

(1)

—

0, 1, 2, 3, 4

0, CL1, or CL2

Improves command 
efficiency.

Write latency

One clock

Read latency – 1

5, 6, 7, or 8

Improves command 
efficiency.

Termination

PCB, discrete to V

TT

Discrete to V

TT

 or ODT Discrete to V

TT

 or ODT 

parallel termination. 

Controlled impedance 

output.

Improves signaling, eases 
PCB layout, reduces system 
cost.

Data strobes

Single-ended

Differential or 

single-ended

Differential 

mandated.

Improves timing margin.

Clock, address, and 
command (CAC) 
layout

Balanced tree

Balanced tree

Series or daisy 

chained

The DDR3 SDRAM read and 
write leveling feature allows 
for a much simplified PCB 
and DIMM layout. You can 
still optionally use the 
balanced tree topology.

Note to 

Table 2

:

(1) The Altera DDR and DDR2 SDRAM high-performance controllers do not support additive latency.

Summary of Contents for Stratix III

Page 1: ...ce Altera Stratix III and Stratix IV devices support DDR3 SDRAM interfaces with dedicated DQS write and read leveling circuitry Table 1 displays the maximum clock frequency for DDR3 SDRAM in Stratix III devices Table 1 DDR3 SDRAM Maximum Clock Frequency Supported in Stratix III Devices Note 1 2 Speed Grade fMAX MHz 2 533 3 3 and I3 400 4 4L and I4L at 1 1 V 333 4 5 4 4L and I4L at 0 9 V Not suppor...

Page 2: ...herwise mentioned Background This section gives background information on the following topics DDR3 SDRAM Overview IOE Dedicated DDR3 SDRAM Features DDR3 SDRAM Interface Termination and Topology ALTMEMPHY Megafunction Overview DDR3 SDRAM Overview DDR3 SDRAM is internally configured as an eight bank DRAM DDR3 SDRAM uses an 8n prefetch architecture to achieve high speed operation The 8n prefetch arc...

Page 3: ...tion by 17 compared to DDR2 SDRAM All DDR3 SDRAM devices have eight internal banks With more banks available the page to hit ratio is twice that of DDR SDRAM DDR3 SDRAM also allows bank interleaving which represents a significant advantage for applications accessing random data Bank interleaving can be extremely effective for concurrent operations and can hide the timing overhead that is otherwise...

Page 4: ...ncreased Prefetch 2 4 8 Lower memory core speed results in higher operating frequency and lower power operation Speed 100 to 200 MHz 200 to 533 MHz 300 to 800 MHz Higher data rate Read latency 2 2 5 3 clocks 3 4 5 clocks 5 6 7 8 9 10 and 11 Eliminating half clock setting allows 8n prefetch architecture Additive latency 1 0 1 2 3 4 0 CL1 or CL2 Improves command efficiency Write latency One clock Re...

Page 5: ...e IOE OCT features ALTPLL megafunction allows you to parameterize the device PLL ALTIOBUF megafunction allows you to parameterize the device IO Device Pin Utilization Table 3 shows the DDR3 SDRAM interface pins and how to connect them to Stratix III pins Table 3 Stratix III DDR3 SDRAM Interface Pin Utilization Part 1 of 2 Pin Pin Planner Symbol Stratix III Pin mem_dq Q DQ mem_dm Q DQ within the re...

Page 6: ...atix III devices per side Address and command Any user I O pin To minimize skew you should place address and command pins in the same bank or side of the device as the following pins mem_clk pins mem_dq mem_dqs mem_dm pins Clock source Dedicated PLL clock input pin with direct not using a global clock net connection to the PLL and optional DLL required by the interface Reset Dedicated clock input ...

Page 7: ...g must be employed Strobes Data DM and Optional ECC Signals The DQS is bidirectional Differential DQS strobe operation enables improved system timing due to reduced crosstalk and less simultaneous switching noise on the strobe output drivers The DQ pins are also bidirectional Regardless of interface width DDR3 SDRAM interfaces can operate in either 4 or 8 mode DQS groups which is dependent on your...

Page 8: ...the rising or falling edge of the address and command clock signal 1 In ALTMEMPHY based solutions the address and command clock ac_clk_1x is always half rate However because of the output enable assertion CS_N CKE and ODT behave like full rate signals even in a half rate PHY PLL and DLL Features and Availability Stratix III devices are well equipped to address the clocking requirements of external...

Page 9: ... data rate registers I O clock divider Programmable delay Read and write leveling one per subbank For example bank 1a 1b and 1c three circuits Figure 1 PLL and DLL Locations and Resources in Stratix III Devices PLL_T1 PLL_T2 PLL_B1 PLL_B2 8A 8B 8C 7C 7B 7A 3A 3B 3C 4C 4B 4A 2A 2B 2C PLL_L3 PLL_L2 1C 1B 1A PLL_R3 PLL_R2 5A 5B 5C 6C 6B 6A 6 6 6 6 6 6 6 6 DLL1 PLL_L1 RCLK 87 82 RCLK 81 76 RCLK 43 38 ...

Page 10: ...he I O clock divider resides adjacent to the DQS logic block In addition to the PLL and read levelled resynchronization clock the I O clock divider can also be fed by the DQS bus or CQn bus 7 The half rate data and clock signals feed into a dual port RAM in the FPGA core 8 You can dynamically change the dataoutbypass signal after configuration DFF I DFF Input Reg A Input Reg B neg_reg_out I D Q D ...

Page 11: ...the write leveling delay chain There is a 90 offset between the DQ write clock and DQS write clock DFF DFF D Q D Q DFF D Q DFF DFF D Q D Q DFF D Q Half Data Rate to Single Data Rate Output Registers DFF DFF D Q D Q DFF D Q Half Data Rate to Single Data Rate Output Enable Registers Alignment Registers 4 Alignment Clock 3 0 1 0 1 0 1 From Core 2 From Core 2 From Core wdata0 2 From Core wdata1 2 From...

Page 12: ...via a dedicated output from the PLL However it may also be clocked directly from the read leveling delay chain The output alignment registers are typically clocked from the PLL 1 Generally alignment and synchronization registers are optional and can be bypassed if not required for ALTMEMPHY based designs these registers are required Regardless of interface speed ALTMEMPHY always implements synchro...

Page 13: ...ence read and write margins can be increased as uncertainties between signals can be minimized 1 ALTMEMPHY based designs do not use dynamic delay chains to deskew interfaces Read and Write Leveling Stratix III I O registers include read and write leveling circuitry to enable skew to be removed or applied to the interface on a DQS group basis There is one leveling circuit located in each I O subban...

Page 14: ... with an effective 100 Ω resistance You can achieve 100 Ω differential termination in one of the following ways 100 Ω single resistor directly between the positive and negative signal 50 Ω single ended resistor to VTT on each positive and negative pin 100 Ω up to VCC and 100 Ω down to ground on each positive and negative pin Electrically all these solutions look the same to differential AC signals...

Page 15: ...ly for DDR3 Single ended or differential DQS mode differential DQS mode for DDR3 Dynamic termination The ALTMEMPHY megafunction automatically parameterizes and initializes your DDR3 SDRAM interface including read and write levelling function and control The ALTMEMPHY megafunction supports an initial calibration sequence to minimize the effect of process variations in the FPGA and memory device Dur...

Page 16: ...the design flow required for Stratix III memory interfaces Select a Device This section discusses the following topics Bandwidth Full or Half Rate SDRAM Controller PLL and Clock Usage Figure 4 Design Flow for Implementing External Memory Interfaces in Stratix III Devices Select Device Instantiate PHY and Controller in a Quartus II Project Determine Board Design Constraints Perform Board Level Simu...

Page 17: ...ff As the structure of memory controllers varies considerably this section uses the ALTMEMPHY architecture where appropriate Bandwidth Before designing any memory interface determine the required bandwidth of the memory interface Bandwidth can be expressed as shown in Equation 1 and Equation 2 After calculating the bandwidth requirements of your system determine which memory type and device to use...

Page 18: ...M minimum operating frequency is 300 MHz The ALTMEMPHY megafunction cannot achieve this frequency in full rate implementations in Stratix III devices PLL and Clock Usage The exact number of clocks and hence PLLs required in your design depends greatly on the memory interface frequency and the IP used 1 Stratix III IOE includes dedicated circuitry for postamble protection which is derived directly ...

Page 19: ...ctions require one global or regional clock and five regional clock nets in Stratix III devices Hence six clocks in total are required Any PLL on any side of a Stratix III device can support a single ALTMEMPHY interface Ideally you should pick a PLL and a PLL input clock pin that are located on the same side of the device as the memory interface pins As each PLL can only connect to four global clo...

Page 20: ...ust come from either dedicated clock input pins located on either side of the DLL or from specific PLL output clocks Any clock running at the memory frequency is valid for the DLLs f For more information on DLLs refer to the External Memory Interfaces chapter in the Stratix III Device Handbook To minimize the number of clocks routed directly on the PCB typically this reference clock is sourced fro...

Page 21: ...ypes operating at the same frequency can easily share a single DLL More may be possible depending on the phase shift required 1 Altera memory IP always specifies a default optimal phase setting to override this setting refer to the respective IP user guide To simplify the interface to core IP connections multiple memory interfaces operating at the same frequency usually share the same system and s...

Page 22: ...ups for external memory interfaces should ideally reside within a single bank but always within the same side of a device High speed memory interfaces in top or bottom versus left or right IOE have different timing characteristics and timing margins are affected However Altera can support interfaces with hybrid data groups that wrap around a corner of the device between vertical and horizontal I O...

Page 23: ... configuration and confirm that it meets timing Address and Command Clock and Other Signals This section describes the following signals Address and command Clock Other signals DDR3 SDRAM Component Additional Pins The largest individual DDR3 SDRAM components typically available are 2GB 8 devices These devices usually require a maximum of 38 pins which can be broken down in the following way 8 DQ p...

Page 24: ...e 8 9 group that includes this 4 group if you are not using DM pins with your differential DQS pins If you fail to correctly instantiate the required number of calibration blocks for your design the Quartus II software automatically adds the calibration blocks during compilation With multiple calibration blocks the Quartus II software does not know which calibration blocks are associated with whic...

Page 25: ...rm Board Level Simulations and Line Simulation This design flow indicates that you determine board design constraints and perform board level simulations at the end of the flow However Altera recommends prelayout SI simulations line simulations should take place before board layout and that you use these parameters and rules during the initial design development cycle Advanced I O timing and board...

Page 26: ...peed interfaces to a board design the quality of the signal at the far end of the board route and the propagation delay in getting there are vital for proper system operation The advanced I O timing option is turned on by default for Stratix III devices Ensure that the overall board trace models are a reasonable approximation for each I O standard on each PCB For high speed complex interfaces like...

Page 27: ...information can be entered on a per net basis if desired but in general a net group basis should be sufficient Multiple nets can be selected at the same time and then have their respective board trace models all entered simultaneously Altera suggests the following net groups mem_clk mem_addr mem_a and mem_ba mem_ctrl mem_cas mem_cke mem_cs_n mem_odt mem_ras_n mem_we_n mem_dq_group0 mem_dq 7 0 mem_...

Page 28: ...r the SDRAM high performance controller the MegaWizard Plug In Manager generates a verify timing script variation_name _phy_report_timing tcl After compiling the design in the Quartus II software run the timing script to produce the timing report for different paths such as write data read data address and command and core entire interface timing paths in the design The verify timing script report...

Page 29: ...rly adjust the address and command clock to be more negative than the default phase setting with respect to the system clock if there is more setup margin f For detailed information about the clocks that the ALTMEMPHY megafunction uses refer to the ALTMEMPHY Megafunction User Guide Determine Board Design Constraints and Perform Board Level Simulations To determine the correct board constraints run...

Page 30: ...AM To further improve signal integrity DDR3 SDRAM supports calibrated output impedance drive control so that the driver can better match the transmission line f For more information on available settings of the ODT the output impedance drive control features and the timing requirements for driving the ODT pin refer to your DDR3 SDRAM datasheet Adjust Termination Drive Strength Altera recommends th...

Page 31: ...gets the Stratix III Memory Demonstration Kit which includes a DIMM module MT9JSF12872AY 1G1BZES This flow applies to any other development kit or PCB 1 The Stratix III Memory Demonstration Kit is not available for purchase 1 Early versions of the Stratix III Memory Demonstration Kit included a MT16JTF25664AY 1G1D1 DDR3 SDRAM DIMM which is a dual rank DIMM and is not supported by ALTMEMPHY based s...

Page 32: ...r This example design uses the DDR3 SDRAM high performance controller which instantiates the ALTMEMPHY megafunction automatically 1 Before you open the MegaWizard Plug In you must add the S3MB1_Derated Micron MT9JSF12872AY 1G1BZES xml file to your installation directory 80 ip ddr3_high_perf lib directory The xml file is is included in the application note zip file To select the DDR3 SDRAM High Per...

Page 33: ... the Memory Setting tab set Speed grade to 2 2 For PLL reference clock frequency enter 100 to match the on board oscillator 3 For Memory clock frequency enter 400 the maximum frequency supported for DDR3 SDRAM interfaces on Stratix III devices 4 For the memory preset select S3MB1_Derated Micron MT9JSF12872AY 1G1BZES which gives a 72 bit wide 1 152 MB 533 MHz DDR3 unbuffered DIMM see Figure 9 Figur...

Page 34: ...Stratix III and Stratix IV Devices November 2008 Altera Corporation 5 To create a memory preset click Modify parameters In the Preset Editor dialog box you can modify the memory presets see Figure 10 Figure 9 Parameterize the DDR3 SDRAM High Performance Controller ...

Page 35: ...and tQHS are often not defined by memory vendors as these values are only of use in static RTD calculations and non DQS capture mode The wizard does not require these parameters so use the default values The tIS tIH tDS and tDH parameters typically require slew rate derating Figure 10 Modify the Memory Presets to Create a Custom Memory ...

Page 36: ...positive edge of the DQS signal must be within 25 90 of the positive edge of the DDR3 SDRAM clock input To achieve this skew requirement ALTMEMPHY based designs always use DDR IOE registers to generate the CK and CK signals 6 To set the ODT settings for the DDR3 SDRAM interface on your board in the Preset Editor select Memory Initialization Options This example does not use the dynamic ODT Rtt_WR ...

Page 37: ...ing analysis shows that 240 is optimal for the Stratix III memory demonstration board The settings in Auto Calibration Simulation Options are for RTL simulation only and are not applicable for gate level simulation 10 Click Finish to generate your MegaCore function variation The MegaWizard Plug In Manager generates all the files necessary for your DDR3 SDRAM controller and generates an example top...

Page 38: ...erates the constraints files for the example design Apply these constraints to the design before compilation Add Timing Constraints When you instantiate an SDRAM high performance controller it generates a timing constraints file variation_name _phy_ddr_timing sdc The timing constraint file constrains the clock and input and output delay on the SDRAM high performance controller To add timing constr...

Page 39: ...d 2 On the Project menu click Set as Top Level Entity Set Optimization Technique To ensure the remaining unconstrained paths are routed with the highest speed and efficiency set the optimization technique to Speed To set the optimization technique follow these steps 1 On the Assignments menu click Settings 2 Select Analysis Synthesis Settings 3 Select Speed under Optimization Technique Click OK Se...

Page 40: ... assign each DQS pin in your design to the required DQS pin in the Pin Planner The Quartus II Fitter then automatically places the respective DQ signals onto suitable DQ pins within each group To see DQS groups in Pin Planner right click select Show DQ DQS Pins and click In x8 x9 Mode Pin Planner shows each DQS group in a different color and with a different legend S DQS pin Sbar DQSn pin and Q DQ...

Page 41: ...ons Pin pairs show a red line between each pin pair 1 You must place mem_clk 0 and mem_clk_n 0 on a DIFFIO_RX pin pair 6 Place the clock_source pin on a dedicated PLL clock input pin with a direct connection to the SDRAM controller PLL and DLL pair usually on the same side of the device as your memory interface This recommendation reduces PLL jitter saves a global clock resource and eases timing a...

Page 42: ...address and command cannot be assigned as virtual pins Advanced I O Timing ALTMEMPHY based designs assume that the memory address and command signals are matched length to the memory clock signals Typically this length match is not true for DIMM based designs You should verify the difference in your design To amend the TimeQuest sdc file variation name _phy_ddr_timing sdc to include this differenc...

Page 43: ...del for both CAC and CLK and CLK are a simplified approximation of the DIMM topology into a lumped load at the far end of the line The use of this simplified model is pending characterization and validation Figure 14 through Figure 17 show a typical board trace model for a CAC mem_clk DQ and DQS pin on the Stratix III memory demonstration board including the data for the MT9JSF12872AY 1G1 memory m...

Page 44: ...ng DDR3 SDRAM in Stratix III and Stratix IV Devices November 2008 Altera Corporation Figure 15 Stratix III Memory Demonstration Board Memory Clock Signal Board Trace Model Figure 16 Stratix III Memory Demonstration Board DQ Signal Board Trace Model ...

Page 45: ..._ length Cn Rns Rnh Length C_per_ length L_per_ length Cf Rfh Rfp Addr 2 2 904 3 5p 8 3n 8 488 3 75p 8 9n 13 5p 39 CLK 3 07 3 1p 9 3n 4 6p 3 8 488 3 75p 8 9n 7 2p 36 CKE CS 2 937 3 5p 8 3n 8 480 3 75p 8 9n 13 5p 39 ODT 2 853 3 5p 8 3n 8 480 3 75p 8 9n 13 5p 39 DQS0 2 905 3 5p 8 3n 15 0 661 3 0p 10 7n 3p 60 DQS1 2 793 3 5p 8 3n 15 0 780 3 0p 10 7n 3p 60 DQS2 2 893 3 5p 8 3n 15 0 913 3 0p 10 7n 3p 6...

Page 46: ...on on compensation capacitors refer to Micron Technical Note TN_47_01 Perform RTL or Functional Simulation Optional This section describes RTL and functional simulation Set Up Simulation Options To set up simulation option follow these steps 1 Obtain and copy the vendors memory model to a suitable location For example obtain the ddr3 v and ddr3_parameters vhd memory model files from the Micron web...

Page 47: ...est Benches 5 Click New 6 Enter a name for the Test bench name 7 Enter the name of the automatically generated testbench variation name _example_top_tb in Top level module in test bench 8 Enter the name of the top level instance in Design instance in test bench 9 Under Simulation period set End simulation to 100 μs 10 Add the testbench files and automatically generated memory model files In the Fi...

Page 48: ...re The report timing script performs the following tasks Creates a timing netlist Reads the sdc file Updates the timing netlist To run the report timing script in the TimeQuest Timing Analyzer window follow these steps 1 Open the panel in the Quartus II software 2 Double click Update Timing Netlist in the left pane which automatically runs Create Timing Netlist and Read SDC After a task is execute...

Page 49: ...andbook f For detailed information about timing analysis refer to AN 438 Constraining and Analyzing Timing for External Memory Interfaces Adjust Constraints For example if the timing margin report shows negative hold time on the address and command datapath adjusting the clock that is regulating the address and command output registers can improve the hold margin on the address and command datapat...

Page 50: ...ng the phase setting The negative hold margin reported is 45 ps Therefore delay clk6 by an amount larger than that Using the frequency of clk6 translate the amount of time delay to degrees in the PLL setting For this example clk6 is 200 MHz which 45 ps translates to 3 To ensure positive margin for hold delay clk6 by more than 3 which means the new phase setting for clk6 is larger than 318 For this...

Page 51: ...es and parallel OCT resistor depending on whether the Stratix III devices are performing a write or a read operation The OCT features offer user mode calibration to compensate for any variation in voltage and temperature during normal operation to ensure that the OCT values remain constant The parallel and series OCT features of the Stratix III devices are available in either a 25 Ω or 50 Ω settin...

Page 52: ... OCT feature of the Stratix III FPGA device In this setup the driver s DDR3 SDRAM output impedance is set to 34 Ω RZQ 7 which combines with the on DIMM series 15 Ω resistor to match the transmission line resulting in optimal signal transmission to the receiver FPGA On the receiver FPGA side it is properly terminated with 50 Ω which matches the impedance of the transmission line thus eliminating an...

Page 53: ...rtus II software may report that the default or chosen drive strength cannot drive the line to the specified toggle rate or minimum pulse width as shown in Figure 24 If you encounter this error use the stronger drive strength I O standard Ensure that you re simulate your design with the new drive strength to ensure that signal quality is still acceptable 1 The Quartus II software v8 1 has a bug th...

Page 54: ...lick SignalTap II Logic Analyzer 2 In the Signal Configuration window next to the Clock box click Browse Node Finder 3 Type phy_clk in the Named box for Filter select SignalTap II pre synthesis and click List 4 Select ddr3_dimm ddr3_dimm_inst phy_clk in Nodes Found and click to add the signal to Selected Nodes 5 Click OK 6 Under Signal Configuration specify the following settings For Sample depth ...

Page 55: ..._write_req pnf pnf_per_byte test_complete trigger ctl_cal_success ctl_cal_fail ctl_wlat ctl_rlat 1 Do not add any DDR3 SDRAM interface signals to the SignalTap II logic analyzer The load on these signals increases and adversely affects the timing analysis 10 Click OK 11 To reduce the SignalTap II logic size turn off Trigger Enable on the following bus signals local_address local_rdata local_wdata ...

Page 56: ... Start Compilation Verify Timing Once the design compiles ensure that TimeQuest timing analysis passes successfully In addition to this FPGA timing analysis check your PCB or system SDRAM timing To run timing analysis run the _phy_report_timing tcl script 1 On the Tools menu click Tcl Scripts 2 Select variation name _phy_report_timing tcl and click Run Connect the Development Board Connect the dev...

Page 57: ... file click the Program Device button see Figure 26 Test the Example Design in Hardware When the example design including SignalTap II successfully downloads to your development board click Run Analysis to run once or click Autorun Analysis to run continuously Figure 27 shows the design analysis Figure 26 Install the SRAM Object File in the SignalTap II Dialog Box Program Device Browse Program Fil...

Page 58: ... Device Handbook External Memory Interfaces chapter of the Stratix IV Device Handbook External DDR Memory PHY Interface ALTMEMPHY Megafunction User Guide DDR3 SDRAM High Performance Controller User Guide ALTDLL and ALTDQ_DQS Megafunctions User Guide AN 520 DDR3 SDRAM Interface Termination and Layout Guidelines AN 462 Implementing Multiple Memory Interfaces Using the ALTMEMPHY Megafunction AN 438 C...

Page 59: ...out notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Corporation Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services Document ...

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