DDR3 SDRAM in Stratix III Devices Design Flow
Page 21
© November 2008
Altera Corporation
AN 436: Using DDR3 SDRAM in Stratix III and Stratix IV Devices
shows the 780-pin package devices PLL and DLL reference clock
connections.
The DLL reference clock should be the same frequency as the memory interface, but
the phase is not important.
The required DQS capture phase is optimally chosen based on operating frequency
and external memory interface type (DDR, DDR2, DDR3, QDRII, or RLDRAM II). As
each DLL supports two possible phase offsets, two different memory interface types
operating at the same frequency can easily share a single DLL. More may be possible,
depending on the phase shift required.
1
Altera memory IP always specifies a default optimal phase setting, to override this
setting, refer to the respective IP user guide.
To simplify the interface to core IP connections, multiple memory interfaces operating
at the same frequency usually share the same system and static clocks as each other
where possible. This sharing minimizes the number of dedicated clock nets required
and reduces the number of different clock domains found within the same design.
Figure 5.
PLL and DLL Reference Clock Connections in 780-pin Package Devices
DLL1
PLL_T1
Optional Clock Connection
DLL2
PLL_B1
PLL_L1
DLL4
DLL3
PLL_R1
Optional Clock Connection
PLL_R4