DDR3 SDRAM in Stratix III Devices Design Flow
Page 27
© November 2008
Altera Corporation
AN 436: Using DDR3 SDRAM in Stratix III and Stratix IV Devices
Board trace models include two transmission line segments (near and far). These line
segments are ideal for SDRAM interfaces. You can use the near transmission line to
represent the PCB and the far transmission line to represent the DIMM.
The board trace model should only include PCB or off chip information. Do not
include the Stratix III I/O pin and package capacitance, OCT, or drive strength
settings, as the Quartus II software ascertains these dynamically.
ODT at the memory should be included as external discreet termination and the
capacitive loading of the memory should be calculated for each net and also added.
1
Ideally, the distributed capacitance and inductance of your PCB traces should be
ascertained from your PCB development tool. However, in general a 50-
Ω
trace is
approximately 3 pF and 8 nH per inch.
Trace delay information can be entered on a per net basis if desired, but in general a
net group basis should be sufficient. Multiple nets can be selected at the same time
and then have their respective board trace models all entered simultaneously.
Altera suggests the following net groups:
■
mem_clk
■
mem_addr
(
mem_a
and
mem_ba
)
■
mem_ctrl
(
mem_cas#
,
mem_cke
,
mem_cs_n
,
mem_odt
,
mem_ras_n
,
mem_we_n
)
■
mem_dq_group0(mem_dq[7..0]
,
mem_dm[0])
■
mem_dq_group1(mem_dq[15..8]
,
mem_dm[1])
■
mem_dq_group
■
mem_dqs0
and
mem_dqsn0
1
The DQS pin can be combined with the respective DQ group as a single-ended signal,
otherwise each differential DQS pin pair should be entered separately.
DIMM board trace models and SDRAM component capacitive loading information
should be obtained from your memory vendor directly and must be included into
your Quartus II board trace model parameters.
More precise board trace models result in more accurate TimeQuest timing analysis.
f
For more information, refer to the
chapter of the
Quartus II Handbook
.
Perform RTL or Functional Simulation (Optional)
After instantiating the SDRAM high-performance controller, it generates an example
design and driver for testing the memory interface.