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DDR3 SDRAM in Stratix III Devices Design Flow
AN 436: Using DDR3 SDRAM in Stratix III and Stratix IV Devices
© November 2008
Altera Corporation
These script files are based on the design name used when instantiating the
ALTMEMPHY megafunction. If you plan to use your own top-level design, you must
edit the scripts to match your custom top-level design.
f
For more information about creating, generating, and setting the constraints for the
design,
External DDR Memory PHY Interface (ALTMEMPHY) Megafunction User
f
To determine which drive strength and termination to use, refer to
SDRAM Interface Termination and Layout Guidelines
Plan Resources
This section describes planning resources.
shows the pin placements that Altera recommends.
The SDRAM high-performance controllers do not generate pin assignments for
non-memory signals such as clock sources or pin location assignments for the design.
Launch
Pin Planner
to make these assignments to the design.
Advanced IO Timing
As part of I/O planning, especially with high-speed designs, you should take
board-level signal integrity and timing into account. When adding an FPGA device
with high-speed interfaces to a board design, the quality of the signal at the far end of
the board route, and the propagation delay in getting there, are vital for proper
system operation.
The advanced I/O timing option is turned on by default for Stratix III devices.
Ensure that the overall board trace models are a reasonable approximation for each
I/O standard on each PCB. For high-speed complex interfaces like DDR3 SDRAM,
ensure that the board trace models are accurate for each specific signal class by using
Pin Planner. Pin Planner includes a GUI schematic representation of the board trace
model that you are modifying.
Table 6.
Stratix III DDR3 SDRAM Pin Placement Recommendations
Signal
Pin on FPGA
Pin on Memory Device
Data (
mem_dq
)
DQ
DQ
Data mask (
mem_dm
)
DQ
DM
Data strobe (
mem_dqs
)
DQS
or
DQSn
DQS
or
DQS#
Memory clock (
mem_clk
)
DQ
, or
DQS
, or
DQSn
CK
or
CK#
Address
Any user I/O
A
or
BA
Command
CS#
,
RAS#
,
CAS#
,
WE#
,
CKE
, or
ODT
Notes to
(1) The
DM
pins must be in the DQ group.
(2) Any unused
DQ
or
DQS
pins with
DIFFIO_RX
capability for
mem_clk[0]
and
mem_clk_n[0]
.
(3) Any unused
DQ
or
DQS
pins with
DIFFOUT
capability for
mem_clk[n:1]
and
mem_clk_n[n:1]
. Where
n
is greater than or equal to 1.
(4) Ensure that address and command pins are placed on the same side of the device as the memory clock pins. Also if OCT is used, ensure that
the
RUP
and
RDN
pins are assigned correctly.