Configuration, Debug, and Extension Options
Table 4-12: System Settings for PCI Express
Parameter
Value
Description
Enable
configuration
via Protocol
(CvP)
On/Off
When On, the Quartus Prime software places the Endpoint in the
location required for configuration via protocol (CvP). For more
information about CvP, click the
Configuration via Protocol (CvP)
link below.
Enable
dynamic
reconfigura‐
tion of PCIe
read-only
registers
On/Off
When On, you can use the Hard IP reconfiguration bus to
dynamically reconfigure Hard IP read
-
only registers. For more
information refer to
Hard IP Reconfiguration Interface
.
Enable Altera
Debug Master
Endpoint
(ADME)
On/Off
When On, you can use the Altera System Console to read and write
the embedded Arria 10 Native PHY registers.
Enable Arria
10 FPGA
Development
Kit connection
On/Off
When On, add control and status conduit interface to the top level
variant, to be connected a PCIe Development Kit component.
Enable link
Inspector
On/Off
When On, the variant includes an internal Link Inspector to
monitor TLP performance on the Avalon-ST interface. You can use
this inspector to observe LTSSM state transitions and latency, and
calculate throughput. The Link Inspector uses the address range
32’h900-32’hFFF. The SR-IOV variant uses this address range to
implement the Shadow Extensions Bus (CSEB). Consequently, the
Link Inspector is not available for SR-IOV variants.
This feature is preliminary in the current release.
Related Information
Arria 10 Transceiver PHY User Guide
Provides information about the ADME feature for Arria 10 devices.
4-14
Configuration, Debug, and Extension Options
UG-01145_avmm_dma
2015.11.02
Altera Corporation
Parameter Settings
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