Byte Offset
Register
Dir
Description
14'h0064
ltssm_reg[4:0]
O
Specifies the current LTSSM state. The LTSSM state
machine encoding defines the following states: :
• 5'b: 00000: Detect.Quiet
• 5'b: 00001: Detect.Active
• 5'b: 00010: Polling.Active
• 5'b: 00011: Polling.Compliance
• 5'b: 00100: Polling.Configuration
• 5'b: 00101: Polling.Speed
• 5'b: 00110: config.Linkwidthstart
• 5'b: 00111: Config.Linkaccept
• 5'b: 01000: Config.Lanenumaccept
• 5'b: 01001: Config.Lanenumwait
• 5'b: 01010: Config.Complete
• 5'b: 01011: Config.Idle
• 5'b: 01100: Recovery.Rcvlock
• 5'b: 01101: Recovery.Rcvconfig
• 5'b: 01110: Recovery.Idle
• 5'b: 01111: L0
• 5'b: 10000: Disable
• 5'b: 10001: Loopback.Entry
• 5'b: 10010: Loopback.Active
• 5'b: 10011: Loopback.Exit
• 5'b: 10100: Hot.Reset
• 5'b: 10101: LOs
• 5'b: 11001: L2.transmit.Wake
• 5'b: 11010: Speed.Recovery
• 5'b: 11011: Recovery.Equalization, Phase 0
• 5'b: 11100: Recovery.Equalization, Phase 1
• 5'b: 11101: Recovery.Equalization, Phase 2
• 5'b: 11110: recovery.Equalization, Phase 3
14'h0068
current_speed_reg[1:0]
O
Indicates the current speed of the PCIe link. The
following encodings are defined:
• 2b’00: Undefined
• 2b’01: Gen1
• 2b’10: Gen2
• 2b’11: Gen3
7-30
Control Register Access (CRA) Avalon-MM Slave Port
UG-01145_avmm_dma
2015.11.02
Altera Corporation
Registers
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