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Physical Layout of Hard IP In Arria 10 Devices

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2015.11.02

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Arria 10 devices include 1–4 hard IP blocks for PCI Express. The bottom left hard IP block includes the

CvP functionality for flip chip packages. For other package types, the CvP functionality is in the bottom

right block.
Note: Arria 10 devices do not support configurations that configure a bottom (left or right) hard IP block

with a Gen3 x4 or Gen3 x8 IP core and also configure the top hard IP block on the same side with a

Gen3 x1 or Gen3 x2 IP core variation.

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of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any

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Summary of Contents for Arria 10 Avalon-ST Interface

Page 1: ... Avalon MM DMA Interface for PCIe Solutions User Guide Last updated for Quartus Prime Design Suite 15 1 Subscribe Send Feedback UG 01145_avmm_dma 2015 11 02 101 Innovation Drive San Jose CA 95134 www altera com ...

Page 2: ...onnecting interfaces for this variant Avalon MM DMA Bridge PCIe Hard IP Block PIPE Interface PHY IP Core for PCIe PCS PMA Serial Data Transmission Application Layer User Logic Avalon MMwith DMAInterface 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent...

Page 3: ...ation about all Altera IP cores including parameterizing generating upgrading and simulating IP Creating Version Independent IP and Qsys Simulation Scripts Create simulation scripts that do not require manual updates for software or IP version upgrades Project Management Best Practices Guidelines for efficient management and portability of your project and IP files PCI Express Base Specification 3...

Page 4: ...a different maximum link rate Dedicated 16 kilobyte KB receive buffer Support for 128 or 256 bit Avalon MM interface to Application Layer with embedded DMA up to Gen3 8 data rate Support for 32 or 64 bit addressing for the Avalon MM interface to the Application Layer Qsys design example demonstrating parameterization design modules and connectivity Extended credit allocation settings to better opt...

Page 5: ...sts 256 8 16 or 256 Automatically handle out of order completions transparent to the Application Layer Not supported Supported Supported Automatically handle requests that cross 4 KB address boundary transparent to the Application Layer Not supported Supported Supported Polarity Inversion of PIPE interface signals Supported Supported Supported Number of MSI requests 1 2 4 8 16 or 32 1 2 4 8 16 or ...

Page 6: ...P Not supported Config Type 1 Read Request CfgRd1 RP RP Not supported Config Type 1 Write Request CfgWr1 RP RP Not supported Message Request Msg EP RP Not supported Not supported Message Request with Data MsgD EP RP Not supported Not supported Completion Cpl EP RP EP RP EP Completion with Data CplD EP RP Not supported EP Completion Locked CplLk EP RP Not supported Not supported Completion Lock wit...

Page 7: ... was included in the previous release Altera reports any exceptions to this verification in the Altera IP Release Notes or clarifies them in the Quartus Prime IP Update tool Altera does not verify compilation with IP core versions older than the previous release Related Information Altera IP Release Notes Device Family Support Table 1 5 Device Family Support Device Family Support Arria 10 Prelimin...

Page 8: ...m stimuli test the Application Layer interface Configuration Space and all types and sizes of TLPs Error injection tests inject errors in the link TLPs and Data Link Layer Packets DLLPs and check for the proper responses PCI SIG Compliance Checklist tests that specifically test the items in the checklist Random tests that test a wide range of traffic patterns Altera provides example designs that y...

Page 9: ...Gen3 x8 256 18000 47 31450 Related Information Fitter Resources Reports Recommended Speed Grades Recommended speed grades are pending characterization of production Arria 10 devices Table 1 7 Arria 10 Recommended Speed Grades for All Avalon MM Widths and Frequencies Lane Rate Link Width Interface Width Application Clock Frequency MHz Recommended Speed Grades Gen1 8 128 Bits 125 1 2 3 4 Gen2 4 128 ...

Page 10: ...rs The Altera testbench and Root Port or Endpoint BFM provide a simple method to do basic testing of the Application Layer logic that interfaces to the variation However the testbench and Root Port BFM are not intended to be a substitute for a full verification environment To thoroughly test your applica tion Altera suggests that you obtain commercially available PCI Express verification IP and to...

Page 11: ...ew design examples These examples help designers like you get more out of the Altera PCI Express IP core and may decrease your time to market The design examples of the Altera Wiki page provide useful guidance for developing your own design However the content of the Altera Wiki is not guaranteed by Altera 1 10 Creating a Design for PCI Express UG 01145_avmm_dma 2015 11 02 Altera Corporation Datas...

Page 12: ...era altera_pcie altera_pcie_a10_ed example_design a10 directory Figure 2 1 Development Steps for the Design Example Example Design Generation Compilation Simulator Functional Simulation Compilation Quartus Prime Hardware Testing Design Example 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Cor...

Page 13: ...lation Script Design Components for the Avalon MM with DMA Testbench Figure 2 3 Block Diagram for the Qsys DMA Design Example Simulation Testbench Root Port BFM pcie_example_design_inst OR Host Memory Descriptors Data Driver Transaction Hard IP for PCIe Data Link and Physical Layers On Chip Memory DMA Data PCI Express Example Design Testbench Descriptor Controller DMA Engine Avalon MM to PCIe TLP ...

Page 14: ... Arria 10 Hard IP for PCI Express Endpoint with the Instantiate internal descriptor controller parameter enabled The automatically generated testbench performs downstream memory reads and writes You can edit the testbench parameters in pcie_example_design_tb v to create a testbench that illustrates the following more advanced DMA features Host allocation of memory Descriptor instructions Upstream ...

Page 15: ...he Avalon MM clock and reset interfaces Generating the Design Figure 2 5 Procedure Start Parameter Editor Specify IP Variation and Select Device Select Design Parameters Initiate Design Generation Specify Design Example 2 4 Generating the Design UG 01145_avmm_dma 2015 11 02 Altera Corporation Arria 10 PCI Express Quick Start Guide Send Feedback ...

Page 16: ...Settings tab 5 On the Example Design tab select either the PIO or DMA design for your IP variation 6 For Example Design Files select the Simulation and Synthesis options 7 For Generated HDL Format only Verilog is available 8 For Target Development Kit select the Arria 10 FPGA Development Kit ES2 option Note SRAM object file sof generation is only supported for Arria 10 ES2 devices in the 15 1 Quar...

Page 17: ...ie_example_ design_tb pcie_example_design_tb sim mentor 1 To run the DMA design example that demonstrates both downstream and upstream traffic open example_design pcie_example_design_tb pcie_ example_design_tb sim pcie_example_design_tb v and change the value of apps_type_hwtcl to 6 2 do msim_setup tcl 3 ld_debug 4 run all 5 A successful simulation ends with the following message Simulation stoppe...

Page 18: ...ollowing message Simulation stopped due to successful completion Cadence example_design pcie_example_ design_tb pcie_example_design_tb sim cadence 1 To run the DMA design example that demonstrates both downstream and upstream traffic open example_design pcie_example_design_tb pcie_ example_design_tb sim pcie_example_design_tb v and change the value of apps_type_hwtcl to 6 2 Create a shell script m...

Page 19: ... Partial Transcript from Successful Avalon MM DMA Simulation Testbench 2 8 Compiling and Simulating the Design UG 01145_avmm_dma 2015 11 02 Altera Corporation Arria 10 PCI Express Quick Start Guide Send Feedback ...

Page 20: ...Examples The software application is available on both 32 and 64 bit Windows platforms This program performs the following tasks 1 Prints the Configuration Space lane rate and lane width 2 Writes 0x00000000 to the specified BAR at offset 0x00000000 to initialize the memory and read it back 3 Writes 0xABCD1234 at offset 0x00000000 of the specified BAR Reads it back and compares If successful the te...

Page 21: ...development board using the generated sof file Tools Programmer d Open the Windows Device Manager and scan for hardware changes e Select the Altera FPGA listed as an unknown PCI device and point to the appropriate 32 or 64 bit driver altera_pice_win_driver inf in the Windows_driver directory f After the driver loads successfully a new device named Altera PCI API Device appears in the Windows Devic...

Page 22: ...he BAR number 0 5 you specified when parameterizing the IP core Note The bus device and function numbers for your hardware setup may be different 5 The test displays the message PASSED if the test is successful Related Information Arria 10 Development Kit Conduit Interface on page 6 27 Arria 10 GX FPGA Development Kit UG 01145_avmm_dma 2015 11 02 Compiling and Testing the Design in Hardware 2 11 A...

Page 23: ...nd maximum read request size for read requests Supports out of order completions when the original request is divided into multiple requests to adhere to the read request size Using the DMA Read and DMA Write modules you can specify descriptor entry table entries with large payloads On Chip Memory IP core This IP core stores the DMA data This 32 KByte memory has a 256 bit data width Descriptor Con...

Page 24: ...gram of Arria 10 Avalon MM DMA for PCI Express Transaction Hard IP for PCIe Data Link and Physical Layers On Chip Memory DMA Data Qsys System Design Arria 10 Hard IP for PCI Express PCI Express Link Descriptor Controller Avalon MM DMA Bridge Arria 10 Hard IP for PCI Express Using Avalon MM Inteface with DMA Interconnect Related Information Arria 10 Avalon MM DMA for PCI Express on page 10 8 DMA De...

Page 25: ...eter Value Testbench System Create testbench Qsys system Standard BFMs for standard Qsys interfaces Create testbench simulation model Verilog Allow mixed language simulation You can leave this option off Output Directory Testbench working_dir ep_g3x8_avmm256_integrated_tb 6 Click Generate Qsys generates the testbench UG 01145_avmm_dma 2015 11 02 Generating the Testbench 3 3 Getting Started with th...

Page 26: ...tpcie_ monitor_ dev _dlhip_tlp_file_log log in your simulation directory Table 3 3 Sample Simulation Log File Entries Time TLP Type Payload Bytes TLP Header 17989 RX CfgRd0 0004 04000001_0000000F_01080008 17989 RX MRd 0000 00000000_00000000_01080000 18021 RX CfgRd0 0004 04000001_0000010F_0108002C 18053 RX CfgRd0 0004 04000001_0000030F_0108003C 18085 RX MRd 0000 00000000_00000000_0108000C Simulatin...

Page 27: ... Prime project with the New Project Wizard which helps you specify the working directory for the project assign the project name and designate the name of the top level design entity 1 On the Quartus Prime File menu click then New Project Wizard then Next 2 Click Next in the New Project Wizard Introduction The introduction does not appear if you previously turned it off 3 On the Directory Name Top...

Page 28: ...RTUAL_PIN ON to pcie_a10_hip_0_hip_pipe_ 4 Save the qsf file Compiling the Design 1 Before compiling you need to make a few changes to your top level Verilog HDL file to create a design that you can successfully download to a PCB a In the project_dir ep_g3x8_avmm256 synth open ep_g3x8_avmm256_integrated v b Comment out the declaration for pcie_a10_hip_0_hip_ctrl_test_in c Add a wire 31 0 pcie_a10_...

Page 29: ... PCI Expess with Avalon MM DMA interface This design example is available in install_dir ip altera altera_pcie altera_pcie_hip_256_avmm example_design dev Figure 3 3 External Descriptor Controller Connectivity UG 01145_avmm_dma 2015 11 02 Descriptor Controller Connectivity when Instantiated Separately 3 7 Getting Started with the Avalon MM DMA Altera Corporation Send Feedback ...

Page 30: ...etween the hard IP Transaction Layer and the Applica tion Layer implemented in the PLD fabric The Application Layer interface frequency 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and lo...

Page 31: ...to the Throughput Optimization chapter for more information about optimizing your design Refer to the RX Buffer Allocation Selections Available by Interface Type below for the availability of these settings by interface type Minimum configures the minimum PCIe specification allowed for non posted and posted request credits leaving most of the RX Buffer space for received completion header and data...

Page 32: ...he minimum PCIe specification allowed amount of completion space leaving most of the RX Buffer space for received requests Select this option when most of the PCIe requests are generated by the other end of the PCIe link and the local application layer logic never or only infrequently generates single read requests This option is recommended for control and status endpoint applications that don t ...

Page 33: ... to the Avalon MM interface without any changes For the Avalon MM interface with DMA this value must be set to 64 Enable control register access CRA Avalon MM slave port On Off Allows read and write access to bridge registers from the interconnect fabric using a specialized slave port This option is required for Requester Completer variants and optional for Completer Only variants Enabling this op...

Page 34: ...our design Turn this option off if you plan to modify or replace the descriptor controller logic in your design Enable burst capabilities for RXM BAR2 port On Off When you turn this option On the BAR2 RX Avalon MM masters is burst capable If BAR2 is 32 bits and Burst capable then BAR3 is not available for other use If BAR2 is 64 bits the BAR3 register holds the upper 32 bits of the address Enable ...

Page 35: ...efetch able it must have the following 2 attributes Reads do not have side effects such as changing the value of the data read Write merging is allowed The 32 bit prefetchable memory and I O address space BARs are only available for the Legacy Endpoint Size N A Qsys automatically calculates the required size after you connect your components Device Identification Registers Table 4 5 Device ID Regi...

Page 36: ...er the PCI Express Base Specification This value is assigned by PCI SIG to the device manufacturer This register is only valid in the Type 0 Endpoint Configuration Space Address offset 0x02C Subsystem Device ID 16 bits 0x00000000 Sets the read only value of the Subsystem Device ID register in the PCI Type 0 Configuration Space Address offset 0x02C Related Information PCI Express Base Specification...

Page 37: ...only to Root Ports and Endpoints that issue requests on their own behalf This parameter must be set to NONE for the Avalon MM with DMA interface Completion timeouts are specified and enabled in the Device Control 2 register 0x0A8 of the PCI Express Capability Structure Version For all other functions this field is reserved and must be hardwired to 0x0000b Four time value ranges are defined Range A...

Page 38: ...nced Error Capabilities and Control Register This parameter requires you to enable the AER capability ECRC generation On Off Off When On enables ECRC generation capability Sets the read only value of the ECRC generation capable bit in the Advanced Error Capabilities and Control Register This parameter requires you to enable the AER capability Enable ECRC forwarding on the Avalon ST interface On Of...

Page 39: ...faces Surprise down reporting Root Port only On Off When your turn this option On an Endpoint supports the optional capability of detecting and reporting the surprise down error condition The error condition is read from the Root Port Not applicable for Avalon MM or Avalon MM DMA interfaces Slot clock configuration On Off When you turn this option On indicates that the Endpoint or Root Port uses t...

Page 40: ...d to map the MSI X table into memory space This field is read only Legal range is 0 5 Pending Bit Array PBA Offset 31 0 Used as an offset from the address contained in one of the function s Base Address registers to point to the base of the MSI X PBA The lower 3 bits of the PBA BIR are set to zero by software to form a 32 bit qword aligned offset This field is read only Pending BAR Indicator 2 0 S...

Page 41: ...or Present MRL Sensor Present Power Controller Present Attention Button Present 0 4 3 2 1 Not applicable for Avalon MM DMA Slot power scale 0 3 Specifies the scale used for the Slot power limit The following coefficients are defined 0 1 0x 1 0 1x 2 0 01x 3 0 001x The default value prior to hardware and firmware initialization is b 00 Writes to this register also cause the port to send the Set_ Slo...

Page 42: ...or Root Ports The default value of this parameter is 64 ns This is the safest setting for most designs Endpoint L1 acceptable latency Maximum of 1 us Maximum of 2 us Maximum of 4 us Maximum of 8 us Maximum of 16 us Maximum of 32 us No limit This value indicates the acceptable latency that an Endpoint can withstand in the transition from the L1 to L0 state It is an indirect measure of the Endpoint ...

Page 43: ... registers Enable Arria 10 FPGA Development Kit connection On Off When On add control and status conduit interface to the top level variant to be connected a PCIe Development Kit component Enable link Inspector On Off When On the variant includes an internal Link Inspector to monitor TLP performance on the Avalon ST interface You can use this inspector to observe LTSSM state transitions and latenc...

Page 44: ...lect the PIO option the generated design includes a target application including only downstream transactions Simulation On Off When On the generated output includes a simulation model Synthesis On Off When On the generated output includes a synthesis model Generated HDL format Verilog Only Verilog HDL is supported Target Development Kit Arria 10 FPGA Development Kit Arria 10 FPGA Development Kit ...

Page 45: ...poration and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right...

Page 46: ...iver Bank Transceiver Bank Transceiver Bank Transceiver Bank Transceiver Bank GXBR4C PCIe Gen3 HIP with CvP PCIe Gen3 HIP PCIe Gen3 HIP PCIe Gen3 HIP GT 115 UF45 GT 090 UF45 GXBL1E GXBL1C GXBL1D GXBL1E GXBL1F GXBL1G GXBL1H GXBL1I GXBL1J GXBR4D GXBR4E GXBR4F GXBR4G GXBR4H GXBR4I GXBR4J GXBR4C GXBR4D GXBR4E GXBR4F GXBR4G GXBR4H GXBR4I GXBR4J Notes 1 Nomenclature of left column bottom transceiver ban...

Page 47: ...r Bank PCIe Gen3 Hard IP with CvP PCIe Gen3 Hard IP PCIe Gen3 Hard IP GT 115 SF45 GT 090 SF45 GXBL1C GXBL1D GXBL1E GXBL1F GXBL1G GXBL1H GXBL1C GXBL1E GXBL1F GXBL1G GXBL1H GXBR4D GXBR4D GXBR4E GXBR4E GXBR4F GXBR4F GXBR4G GXBR4G GXBR4H GXBR4H GXBR4I GXBR4I Notes 1 Nomenclature of left column bottom transceiver banks always begins with C 2 Nomenclature of right column bottom transceiver banks may beg...

Page 48: ...of left column bottom transceiver banks always begins with C 2 These devices have transceivers only on left hand side of the device 1 PCIe Gen1 Gen3 Hard IP PCIe Gen1 Gen3 with CvP Hard IP Legend PCIe Gen1 Gen3 Hard IP blocks with CvP capabilities PCIe Gen1 Gen3 Hard IP blocks without CvP capabilities Refer to the Arria 10 Transceiver Layout in the Arria 10 Transceiver PHY User Guide for comprehen...

Page 49: ... HIP block that supports CvP txvr_block_N is GXB1C and txvr_block_N 1 is GXB1D Figure 5 4 Arria 10 Gen1 Gen2 and Gen3 x1 Channel and Pin Placement PMA Channel 5 PMA Channel 4 PMA Channel 3 PMA Channel 2 PMA Channel 0 PMA Channel 3 PMA Channel 2 PMA Channel 1 PMA Channel 0 PCS Channel 5 PCS Channel 4 PCS Channel 3 PCS Channel 2 PCS Channel 0 PCS Channel 3 PCS Channel 2 PCS Channel 1 PCS Channel 0 H...

Page 50: ...Channel 0 Hard IP for PCIe Hard IP Ch0 PMA Channel 1 PCS Channel 1 PMA Channel 4 PCS Channel 4 PMA Channel 5 PCS Channel 5 PMA Channel 2 PCS Channel 2 txvr_block_N _TX RX_CH4N txvr_block_N _TX RX_CH5N txvr_block_N 1 _TX RX_CH0N txvr_block_N 1 _TX RX_CH1N txvr_block_N 1 _TX RX_CH2N txvr_block_N 1 _TX RX_CH3N txvr_block_N 1 _TX RX_CH4N txvr_block_N 1 _TX RX_CH5N Channel Placement and fPLL Usage for ...

Page 51: ...nnel 2 PCS Channel 1 PCS Channel 0 Hard IP Ch0 PMA Channel 1 PCS Channel 1 PMA Channel 4 PCS Channel 4 PMA Channel 5 PCS Channel 5 Hard IP for PCIe fPLL1 ATX1 PLL fPLL0 ATX0 PLL ATX1 PLL fPLL0 ATX0 PLL fPLL1 Master CGB Master CGB indicates the location of the master clock generation block CGB Figure 5 10 Arria 10 Gen1 and Gen2 x4 Channel Placement PMA Channel 5 PMA Channel 4 PMA Channel 3 PMA Chan...

Page 52: ... an ATX PLL to generate the 8 0 Gbps clock In these figures channels that are not used for the PCI Express protocol are available for other protocols Unused channels are shown in gray Note In all configurations physical channel 4 in the PCS connects to logical channel 0 in the hard IP You cannot change the channel placements illustrated below Figure 5 12 Arria 10 Gen3 x1 Channel Placement PMA Chan...

Page 53: ...nnel 4 PCS Channel 3 PCS Channel 2 PCS Channel 1 PCS Channel 0 Hard IP for PCIe fPLL1 ATX1 PLL fPLL0 ATX0 PLL fPLL1 ATX1 PLL fPLL0 ATX0 PLL Hard IP Ch0 PMA Channel 1 PCS Channel 1 PMA Channel 2 PCS Channel 2 Master CGB Master CGB indicates the location of the master clock generation block CGB Figure 5 15 Gen3 x8 Channel Placement PMA Channel 5 PMA Channel 4 PMA Channel 3 PMA Channel 0 PMA Channel ...

Page 54: ...ustrates this variant when the DMA Descriptor Controller is instantiated separately Depending on the device the interface to the Application Layer can be 128 or 256 bits 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in othe...

Page 55: ...AR Test and Mode Control test_in 31 0 simu_mode_pipe Gen3PIPE simulation only currentcoeff0 17 0 currentrxpreset0 2 0 eidleinfersel 2 0 phystatus0 powerdown0 1 0 rate 1 0 rxblkst0 rxdata0 31 0 rxdatak 3 0 rxdataskip rxelecidle0 rxpolarity rxstatus0 2 0 rxsynchd0 1 0 rxvalid0 sim_ltssmstate 4 0 sim_pipe_pclk_in sim_pipe_rate 1 0 txblkst txcompl0 txdata0 31 0 txdatak0 3 0 txdataskip txdeemph0 txdete...

Page 56: ...d_i WrAstRxReady_o WrAstTxData_o 31 0 WrAstTxValid_o Descriptor Instructions from Descriptor Controller to DMA Engine RdAstTxData_o 31 0 RdAstTxValid_o Gen3PIPE simulation only currentcoeff0 17 0 currentrxpreset0 2 0 eidleinfersel 2 0 phystatus0 powerdown0 1 0 rate 1 0 rxblkst0 rxdata0 31 0 rxdatak 3 0 rxdataskip rxelecidle0 rxpolarity rxstatus0 2 0 rxsynchd0 1 0 rxvalid0 sim_ltssmstate 4 0 sim_pi...

Page 57: ...dress space RdDmaAddress_o 63 0 Output Specifies the write address in the Avalon MM address space for the read completion data RdDmaWriteData_o 127 or 255 0 Output The read completion data to be written to the Avalon MM address space RdDmaBurstCount_o 4 0 or 5 0 Output Specifies the burst count in 128 or 256 bit words This bus is 5 bits for the 256 bit interface It is 6 bits for the 128 bit interf...

Page 58: ...t words This bus is 5 bits for the 256 bit interface It is 6 bits for the 128 bit interface WrDmaWaitRequest_i Input When asserted indicates that the memory is not ready to be read WrDmaReadDataValid_i Input When asserted indicates that WrDmaReadData_i is valid Figure 6 4 Write DMA Avalon MM Master Reads Data from FPGA Memory write_data_mover WrDmaAddress_o 63 0 write_data_mover WrDmaBurstCount_o ...

Page 59: ...e w 1 2 Bits 1 and 0 have a value of 0 w can be 32 or 64 RxmBurstCount_ n _ o 5 0 Output Specifies the burst count in dwords 32 bits This optional signal is available for BAR2 when you turn on Enable burst capabili ties for RXM BAR2 ports RxmByteEnable_ n _ o w 0 Output Specifies the valid bytes of data to be written w has the following values 4 for the non bursting RX Master 32 for the bursting 1...

Page 60: ...l Name Direction Description TxsChipSelect_i Input When asserted indicates that this slave interface is selected TxsRead_i Input When asserted specifies a TX Avalon MM slave read request from the Root Complex or Root Port TxsWrite_i Input When asserted specifies a TX Avalon MM slave write request to the Root Complex or Root Port TxsWriteData_i w 1 0 Input Specifies the Avalon MM data for a write c...

Page 61: ...Avalon MM DMA bridge Table 6 5 Avalon MM CRA Slave Interface Signals Signal Name Direction Description CraRead_i Input Read enable CraWrite_i Input Write request CraAddress_i 13 0 Input An address space of 16 KB is allocated for the control registers Avalon MM slave addresses provide address resolution down to the width of the slave data bus Because all addresses are byte addresses this address lo...

Page 62: ...ngine Signal Name Direction Description RdAstRxData_i 159 0 Input Specifies the descriptors for the Read DMA module Refer to DMA Descriptor Format table below for bit definitions RdAstRxValid_i Input When asserted indicates that RdAstRxData_i 159 0 is valid RdAstRxReady_o Output When asserted indicates that the Read DMA read module is ready to receive a new descriptor Table 6 7 Descriptor Instruct...

Page 63: ...ription 31 0 Source Low Address Low order 32 bits of the DMA source address The address boundary must align to the 32 bits so that the 2 least significant bits are 2 b00 For the Read DMA module the source address is the PCIe domain address For the Write DMA module the source address is the Avalon MM domain address You must program the low order 32 bits of the address after you program the high ord...

Page 64: ...When asserted a single DMA descriptor has completed success fully 7 0 Descriptor ID The ID of the descriptor whose status is being reported Descriptor Controller Interfaces when Instantiated Internally Read Descriptor Controller Avalon MM Master Port The Read Descriptor Controller Avalon MM master port drives the TX Avalon MM slave port This port drives single dword transactions to the Arria 10 Av...

Page 65: ...led Signal Name Direction Description WrDCMAddress_o 63 0 Output Specifies the address for the write data WrDCMByteEnable_ o 3 0 Output Specifies which data bytes are valid WrDCMReadDataValid_i Input When asserted indicates that the read data is valid WrRdDCMReadData_ o 31 0 Output Holds the single dword read data WrDCMRead_o Output When asserted indicates a read transaction WrDCMWaitRequest_i Inp...

Page 66: ...tor Controller Avalon MM Master Interface Host software writes descriptors to the Avalon MM slave port of the descriptor table This port connects to a bursting DMA write master interface Signal Name Direction Description WrDTSAddress_i 7 0 Input Specifies the descriptor address for the write data WrDTSBurstCount_ i 4 0 or 5 0 Input Specifies the burst count in 128 or 256 bit words WrDTSChipSelect_...

Page 67: ... you do not drive a soft reset signal from the Application Layer this signal must be derived from pin_perst You cannot disable this signal Resets the entire IP Core and transceiver Asynchronous This signal is edge not level sensitive consequently you cannot use a low value on this signal to hold custom logic in reset For more information about the reset controller refer to Reset nreset_status Outp...

Page 68: ...ation about these pins The PCI Express Card Electromechanical Specification 2 0 specifies this pin requires 3 3 V You can drive this 3 3V signal to the nPERST even if the VVCCPGM of the bank is not 3 3V if the following 2 conditions are met The input signal meets the VIH and VIL specification for LVTTL The input signal meets the overshoot specification for 100 C operation as defined in the device ...

Page 69: ... 2 dlup Output When asserted indicates that the Hard IP block is in the Data Link Control and Management State Machine DLCMSM DL_ Up state dlup_exit Output This signal is asserted low for one pld_clk cycle when the IP core exits the DLCMSM DL_Up state indicating that the Data Link Layer has lost communication with the other end of the PCIe link and left the Up state When this pulse is asserted the...

Page 70: ...RX buffer space is finite ko_cpl_spc_header is a static signal that indicates the total number of completion headers that can be stored in the RX buffer l2_exit Output L2 exit This signal is active low and otherwise remains high It is asserted for one cycle changing value from 1 to 0 and back to 1 after the LTSSM transitions from l2 idle to detect When this pulse is asserted the Application Layer ...

Page 71: ...For more information refer to Uncorrectable Internal Error Status Register You must reset the Hard IP if this error occurs because parity errors can leave the Hard IP in an unknown state tx_par_err 1 0 Output When asserted for a single cycle indicates a parity error during TX TLP transmission These errors are logged in the VSEC register The following encodings are defined 2 b10 A parity error was ...

Page 72: ...t This mechanism allows host software to avoid continuous polling of the status table done bits Table 6 19 MSI Interrupt Signal Direction Description MSIIntfc_o 81 0 Output This bus provides the following MSI address data and enabled signals MSIIntfc_o 81 Master enable MSIIntfc_o 80 MSI enable MSIIntfc_o 79 64 MSI data MSIIntfc_o 63 0 MSI address MSIXIntfc_o 15 0 Output Provides for system softwar...

Page 73: ... repeat device enumeration of the PCI Express link after changing the value of read only configuration registers of the Hard IP Table 6 20 Hard IP Reconfiguration Signals Signal Direction Description hip_reconfig_clk Input Reconfiguration clock The frequency range for this clock is 100 125 MHz hip_reconfig_rst_n Input Active low Avalon MM reset Resets all of the dynamic reconfi guration registers ...

Page 74: ...c reconfiguration Drive this signal low 4 clock cycles after the release of ser_shif t_load Figure 6 8 Hard IP Reconfiguration Bus Timing of Read Only Registers avmm_clk hip_reconfig_rst_n user_mode ser_shift_load interface_sel avmm_wr avmm_wrdata 15 0 avmm_rd avmm_rdata 15 0 D0 D0 D1 D1 D2 D3 324 ns 4 clks 4 clks 4 clks For a detailed description of the Avalon MM protocol refer to the Avalon Memo...

Page 75: ...ct the Hard IP for PCI Express on the left side of the device to appropriate channels on the left side of the device as specified in the Pin out Files for Altera Devices Related Information Physical Layout of Hard IP In Arria 10 Devices on page 5 1 Pin out Files for Altera Devices PIPE Interface Signals These PIPE signals are available for Gen1 Gen2 and Gen3 variants so that you can simulate using...

Page 76: ...0xx Electrical Idle Inference not required in current LTSSM state 3 b100 Absence of COM SKP Ordered Set the in 128 us window for Gen1 or Gen2 3 b101 Absence of TS1 TS2 Ordered Set in a 1280 UI interval for Gen1 or Gen2 3 b110 Absence of Electrical Idle Exit in 2000 UI interval for Gen1 and 16000 UI interval for Gen2 3 b111 Absence of Electrical idle exit in 128 us window for Gen1 phystatus0 Input ...

Page 77: ... n This symbol indicates symbol lock and valid data on rxdata n and rxdatak n sim_pipe_ ltssmstate0 4 0 Input and Output LTSSM state The LTSSM state machine encoding defines the following states 5 b00000 Detect Quiet 5 b 00001 Detect Active 5 b00010 Polling Active 5 b 00011 Polling Compliance 5 b 00100 Polling Configuration 5 b00101 Polling Speed 5 b00110 Config LinkwidthsStart 5 b 00111 Config Li...

Page 78: ...data0 31 0 Output Transmit data This bus transmits data on lane n txdatak0 3 0 Output Transmit data control n This signal serves as the control bit for txdata n Bit 0 corresponds to the lowest order byte of rxdata and so on A value of 0 indicates a data byte A value of 1 indicates a control byte For Gen1 and Gen2 only txdataskip0 Output For Gen3 operation Allows the MAC to instruct the TX interfac...

Page 79: ...from the Link Control 2 Register Available for simulation only txswing0 Output When asserted indicates full swing for the transmitter voltage When deasserted indicates half swing txsynchd0 1 0 Output For Gen3 operation specifies the block type The following encodings are defined 2 b01 Ordered Set Block 2 b10 Data Block 6 26 PIPE Interface Signals UG 01145_avmm_dma 2015 11 02 Altera Corporation IP ...

Page 80: ...e compliance mode When set prevents the LTSSM from entering compliance mode Toggling this bit controls the entry and exit from the compliance state enabling the transmission of Gen1 Gen2 and Gen3 compliance patterns 6 Forces entry to compliance mode when a timeout is reached in the polling active state and not all lanes have detected their exit condition 7 Disable low power state negotiation Alter...

Page 81: ...l2_exit devkit_status 22 19 lane_act 3 0 devkit_status 27 23 ltssmstate 4 0 devkit_status 35 28 ko_cpl_spc_header 7 0 devkit_status 47 36 ko_cpl_spc_data 11 0 devkit_status 48 rxfc_cplbuf_ovf devkit_status 49 reset_status devkit_status 255 50 Reserved devkit_ctrl 255 0 Input The devkit_ctrl 255 0 bus comprises the following status signals You can optionally connect these pins to an on board switch...

Page 82: ...nt Capability Structure 0x080 0x0B8 PCI Express Capability Structure PCI Express Capability Structure 0x0B8 0x0FC Reserved N A 0x094 0x0FF Root Port N A 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All o...

Page 83: ... arbitration table Reserved Port Arbitration Table 0x380 0x3BC Port VC6 arbitration table Reserved Port Arbitration Table 0x3C0 0x3FC Port VC7 arbitration table Reserved Port Arbitration Table 0x400 0x7FC Reserved PCIe spec corresponding section name 0x800 0x834 Advanced Error Reporting AER optional Advanced Error Reporting Capability 0x838 0xFFF Reserved N A 0x000 Device ID Vendor ID Type 0 Confi...

Page 84: ...er Type 1 Configuration Space Header Primary Bus Number 0x01C Base Address 3 Secondary Status I O Limit I O Base Base Address Registers Secondary Status Register Type 1 Configuration Space Header 0x020 Base Address 4 Memory Limit Memory Base Base Address Registers Type 1 Configuration Space Header 0x024 Base Address 5 Prefetchable Memory Limit Prefetchable Memory Base Base Address Registers Prefet...

Page 85: ...fset BIR MSI and MSI X Capability Structures 0x070 Pending Bit Array PBA Offset BIR MSI and MSI X Capability Structures 0x078 Capabilities Register Next Cap PTR Cap ID PCI Power Management Capability Structure 0x07C Data PM Control Status Bridge Extensions Power Management Status Control PCI Power Management Capability Structure 0x800 PCI Express Enhanced Capability Header Advanced Error Reporting...

Page 86: ...nd Layout Endpoints store configuration data in the Type 0 Configuration Space The Correspondence between Configuration Space Registers and the PCIe Specification on page 7 1 lists the appropriate section of the PCI Express Base Specification that describes these registers 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 0x028 0x02C 0x030 0x034 0x038 0x03C Device ID Vendor ID Status Com...

Page 87: ...mory Limit Memory Base Prefetchable Base Upper 32 Bits Prefetchable Limit Upper 32 Bits I O Limit Upper 16 Bits I O Base Upper 16 Bits Reserved Capabilities Pointer Expansion ROM Base Address Bridge Control Interrupt Pin Interrupt Line Prefetchable Memory Limit Prefetchable Memory Base PCI Express Capability Structures Figure 7 3 MSI Capability Structure 0x050 0x054 0x058 Message Control Configura...

Page 88: ...PCI Express Enhanced Capability Register Uncorrectable Error Severity Register Uncorrectable Error Mask Register 0x808 0x80C 0x810 0x814 0x818 0x81C 0x82C 0x830 0x834 Correctable Error Status Register Correctable Error Mask Register Advanced Error Capabilities and Control Register Header Log Register Root Error Command Register Root Error Status Register Error Source Identification Register Correc...

Page 89: ...nd detailed internal error reporting 0x200 0x204 Next Capability Offset Version VSEC Length 31 20 19 16 15 8 7 0 Altera DefinedVSEC Capability Header VSEC ID Altera Defined Vendor Specific Header VSEC Revision Altera Marker 0x208 JTAG Silicon ID DW0 JTAG Silicon ID 0x20C JTAG Silicon ID DW1 JTAG Silicon ID 0x210 JTAG Silicon ID DW2 JTAG Silicon ID 0x214 JTAG Silicon ID DW3 JTAG Silicon ID 0x218 Cv...

Page 90: ... Description Value Access 15 0 VSEC ID A user configurable VSEC ID User entered RO 19 16 VSEC Revision A user configurable VSEC revision Variable RO 31 20 VSEC Length Total length of this structure in bytes 0x044 RO Table 7 4 Altera Marker Register Bits Register Description Value Access 31 0 Altera Marker This read only register is an additional marker If you use the standard Altera Programmer sof...

Page 91: ...4 PLD_CLK_IN_USE From clock switch module to fabric This status bit is provided for debug Variable RO 23 CVP_CONFIG_DONE Indicates that the FPGA control block has completed the device configuration via CvP and there were no errors Variable RO 22 Reserved Variable RO 21 USERMODE Indicates if the configurable FPGA fabric is in user mode Variable RO 20 CVP_EN Indicates if the FPGA control block has e...

Page 92: ...The following encodings are defined 1 Selects internal clock from PMA which is required for CVP_ MODE 0 Selects the clock from soft logic fabric This setting should only be used when the fabric is configured in USER_MODE with a configuration file that connects the correct clock To ensure that there is no clock switching during CvP you should only change this value when the Hard IP for PCI Express ...

Page 93: ... the device 0x00000000 RW Table 7 10 CvP Programming Control Register This register is written by the programming software to control CvP programming Bits Register Description Reset Value Access 31 2 Reserved 0x0000 RO 1 START_XFER Sets the CvP output to the FPGA control block indicating the start of a transfer 1 b0 RW 0 CVP_CONFIG When asserted instructs that the FPGA control block begin a transf...

Page 94: ...WS Uncorrectable Internal Error Status Register Table 7 12 Uncorrectable Internal Error Status Register This register reports the status of the internally checked errors that are uncorrectable When specific errors are enabled by the Uncorrectable Internal Error Mask register they are handled as Uncorrectable Internal Errors as defined in the PCI Express Base Specification 3 0 This register is for ...

Page 95: ... RX to Configuration Space bus interface 0 RW1CS 2 When set indicates a parity error was detected at input to the RX Buffer 0 RW1CS 1 When set indicates a retry buffer uncorrectable ECC error 0 RW1CS 0 When set indicates a RX buffer uncorrectable ECC error 0 RW1CS Related Information PCI Express Base Specification 3 0 Correctable Internal Error Mask Register Table 7 13 Correctable Internal Error M...

Page 96: ...ich is reported as correctable This bit is set whenever a CVP_CONFIG_ERROR occurs while in CVP_MODE 0 RW1CS 4 2 Reserved 0 RO 1 When set the retry buffer correctable ECC error status indicates an error 0 RW1CS 0 When set the RX buffer correctable ECC error status indicates an error 0 RW1CS Related Information PCI Express Base Specification 3 0 DMA Descriptor Controller Registers The DMA Descriptor...

Page 97: ...ptor Controller Altera FPGA Memory Read DMA Write DMA Hard IP for PCIe RX Master TX Slave DMA Descriptor Controller Avalon MM Burst Master 256 Bits Avalon MM Master 256 Bits Avalon MM Master Single DWORD Avalon MM Slave Single DWORD Avalon ST Control Status Avalon ST 256 Bits PCIe Avalon MM DMA Bridge Hard IP for PCIe Using Avalon MM Interface with External Descriptor Controller Qsys System The Re...

Page 98: ... are stored immediately after the status entries at offset 0x200 from the values programmed into the RC Read Descriptor Base and RC Write Descriptor Base registers The status and descriptor table must be located on a 32 byte boundary in Root Complex memory Note For example if 128 descriptors are specified and all of them execute then 127 is written to the RD_DMA_LAST_PTR or WR_DMA_LAST_PTR registe...

Page 99: ...t program this register after programming the upper 32 bits at offset 0x4 To change the RC Read Status and Descriptor Base Low base address all descriptors specified by the RD_TABLE_SIZE must be exhausted 0x0004 RC Read Status and Descriptor Base High R W Specifies the upper 32 bits of the base address of the read status and descriptor table in the Root Complex memory Software must program this re...

Page 100: ...ID of the last descriptor requested The difference between the value read and the value written is the number of descriptors to be processed For example if the value reads 4 the last descriptor requested is 4 To specify 5 more descriptors software should write a 9 into the RD_DMA_LAST_PTR register The DMA executes 5 more descriptors The descriptor ID loops back to 0 after reaching RD_TABLE_SIZE Fo...

Page 101: ...ptors specified by the WR_TABLE_SIZE must be exhausted 0x0104 RC Write Status and Descriptor Base High R W Specifies the upper 32 bits of the base address of the write status and descriptor table in the Root Complex memory Software must program this register before programming the lower 32 bit register at offset 0x100 0x0108 EP Write Status and Descriptor FIFO Base Low RW Specifies the lower 32 bi...

Page 102: ... descriptors software should write a 9 into the RD_DMA_LAST_PTR register The DMA executes 5 more descriptors The Descriptor ID loops back to 0 after reaching WR_TABLE_SIZE For example if the WR_TABLE_SIZE value read is 126 and you want to execute three more descriptors software must write 127 and then 1 into the WR_DMA_LAST_PTR register 0x0114 WR_TABLE_SIZE RW Specifies the size of the Read descri...

Page 103: ...ower dword of the read DMA destination address Specifies the address in the Avalon MM domain to which the Read DMA writes data 0x0C RD_CTRL_HIGH_DEST_ADDR Upper dword of the read DMA destination address Specifies the address in the Avalon MM domain to which the Read DMA writes data 0x10 CONTROL Specifies the following information 31 25 Reserved must be 0 24 18 ID Specifies the Descriptor ID Descri...

Page 104: ...e in dwords Must be non zero To enhance performance and reduce internal buffers the transfer size is limited to 8 KB 0x14 0x1C Reserved N A Read DMA Example The following example moves three data blocks from the PCIe address space to the Avalon MM address space Host software running on an embedded CPU allocates the memory and creates the descriptor table in PCIe address space The following figures...

Page 105: ...ed a Each descriptor is 32 bytes The three descriptors require 96 bytes of memory b Each entry in the status table is 4 bytes The 128 entries require 512 bytes of memory The total memory allocation for the status and descriptor tables is 608 bytes 2 Allocate 608 bytes of memory Assume that the start address of the allocated memory is 0xF000_0000 3 Create the descriptor table in the PCI Express add...

Page 106: ...us and descriptor tables The Read DMA automatically adds an offset of 0x200 to this value to start the copy after the status table 7 Program the DMA Descriptor Controller with the on chip FIFO address This is the address to which the Descriptor Controller will copy the status and descriptor table a Program 0x0 to offset 0xC This is the upper 32 bits of the on chip FIFO address in the Avalon MM add...

Page 107: ...dule should read The destination address is the Root Port memory space allocated in Step 3 Specify the DMA length in dwords Assuming a base address of 0x100 for the Write DMA the following assignments illustrate construction of a write descriptor a RD_RC_LOW_SRC_ADDR 0x0100 The base address for the read descriptor table in the Root Port b WD_RC_HIGH_SRC_ADDR 0x0104 c WD_CTLR_LOW_DEST_ADDR 0x0108 d...

Page 108: ...after the initial link training to Gen1 L0 state Retraining directs the LTSSM to the Recovery state Retraining to a higher data rate is not automatic even if both devices on the link are capable of a higher data rate 14 h000C cfg_link_ctrl2 15 0 O cfg_link_ctrl2 31 16 is the secondary Link Control register of the PCI Express capability structure for Gen2 operation When tl_cfg_addr 2 tl_cfg_ctl ret...

Page 109: ...n Root Port mode 14 h0034 cfg_np_bas 11 0 O The non prefetchable memory base register of the Type1 Configuration Space This register is only available in Root Port mode 14 h0038 cfg_np_lim 11 0 O The non prefetchable memory limit register of the Type1 Configuration Space This register is only available in Root Port mode 14 h003C cfg_pr_bas_low 31 0 O The lower 32 bits of the prefetchable base regi...

Page 110: ...g The Application Layer uses this signal to generate a TLP mapped to the appropriate channel based on the traffic class of the packet The following encodings are defined cfg_tcvcmap 2 0 Mapping for TC0 always 0 cfg_tcvcmap 5 3 Mapping for TC1 cfg_tcvcmap 8 6 Mapping for TC2 cfg_tcvcmap 11 9 Mapping for TC3 cfg_tcvcmap 14 12 Mapping for TC4 cfg_tcvcmap 17 15 Mapping for TC5 cfg_tcvcmap 20 18 Mappin...

Page 111: ... Rcvlock 5 b 01101 Recovery Rcvconfig 5 b 01110 Recovery Idle 5 b 01111 L0 5 b 10000 Disable 5 b 10001 Loopback Entry 5 b 10010 Loopback Active 5 b 10011 Loopback Exit 5 b 10100 Hot Reset 5 b 10101 LOs 5 b 11001 L2 transmit Wake 5 b 11010 Speed Recovery 5 b 11011 Recovery Equalization Phase 0 5 b 11100 Recovery Equalization Phase 1 5 b 11101 Recovery Equalization Phase 2 5 b 11110 recovery Equaliz...

Page 112: ...l indicates the number of lanes that configured during link training The following encodings are defined 4 b0001 1 lane 4 b0010 2 lanes 4 b0100 4 lanes 4 b1000 8 lanes UG 01145_avmm_dma 2015 11 02 Control Register Access CRA Avalon MM Slave Port 7 31 Registers Altera Corporation Send Feedback ...

Page 113: ... words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Alte...

Page 114: ...n This reset sequence includes the following steps 1 After pin_perst or npor is released the Hard IP reset controller waits for pld_clk_inuse to be asserted 2 csrt and srst are released 32 cycles after pld_clk_inuse is asserted 3 The Hard IP for PCI Express deasserts the reset_status output to the Application Layer 4 The altpcied_ device v_hwtcl sv deasserts app_rstn 32 pld_clkcycles after reset_s...

Page 115: ...e Detect Active state to the Polling Active state 4 The Hard IP for PCI Express asserts rx_digitalreset The rx_digitalreset signal is deasserted after rx_signaldetect is stable for a minimum of 3 ms Figure 8 4 TX Transceiver Reset Sequence npor pll_locked npor_serdes 127 cycles tx_digitalreset The TX transceiver reset sequence includes the following steps 1 After npor is deasserted the IP core dea...

Page 116: ...rdance with the PCI Express Base Specification you must provide a 100 MHz reference clock that is connected directly to the transceiver Related Information PCI Express Base Specification 3 0 Clock Domains Figure 8 5 Clock Domains and Clock Generation for the Application Layer The following illustrates the clock domains when using coreclkout_hip to drive the Application Layer and the pld_clk of the...

Page 117: ...e interface to achieve a lower throughput Link Width Max Link Rate Avalon Interface Width coreclkout_hip 8 Gen1 128 125 MHz 4 Gen2 128 125 MHz 8 Gen2 128 250 MHz 8 Gen2 256 125 MHz 4 Gen3 128 250 MHz 4 Gen3 256 125 MHz 8 Gen3 256 250 MHz pld_clk coreclkout_hip can drive the Application Layer clock along with the pld_clk input to the IP core The pld_clk can optionally be sourced by a different cloc...

Page 118: ...ency Clock Domain refclk 100 MHz SERDES transceiver Dedicated free running input clock to the SERDES block 8 6 Clock Summary UG 01145_avmm_dma 2015 11 02 Altera Corporation Arria 10 Reset and Clocks Send Feedback ...

Page 119: ...uch errors whether to reset the link or implement other means to minimize the problem Related Information PCI Express Base Specification 3 0 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words a...

Page 120: ...arity Error Deskew error caused by overflow of the multilane deskew FIFO Control symbol received in wrong lane Data Link Layer Errors Table 9 3 Errors Detected by the Data Link Layer Error Type Description Bad TLP Correctable This error occurs when a LCRC verification fails or when a sequence number error occurs Bad DLLP Correctable This error occurs when a CRC verification fails Replay timer Corr...

Page 121: ...er abort status In all cases the TLP is deleted in the Hard IP block and not presented to the Application Layer Unsupported Request for Endpoints Uncorrectable non fatal This error occurs whenever a component receives any of the following Unsupported Requests Type 0 Configuration Requests for a non existing function Completion transaction for which the Requester ID does not match the bus device an...

Page 122: ...tion The Hard IP block handles the following conditions The Requester ID in the completion packet does not match the Configured ID of the Endpoint The completion packet has an invalid tag number Typically the tag used in the completion packet exceeds the number of tags specified The completion packet has a tag that does not match an outstanding request The completion packet for a request that was ...

Page 123: ... which the type and length fields do not correspond with the total length of the TLP A TLP in which the combination of format and type is not specified by the PCI Express specification A request specifies an address length combination that causes a memory space access to exceed a 4 KByte boundary The Hard IP block checks for this violation which is considered optional by the PCI Express specificat...

Page 124: ... Error Conditions Status Bit Conditions Detected parity error status register bit 15 Set when any received TLP is poisoned Master data parity error status register bit 8 This bit is set when the command register parity enable bit is set and one of the following conditions is true The poisoned bit is set during the transmission of a Write Request TLP The poisoned bit is set on a received completion...

Page 125: ...l Protocol Status PoisonedTLP Status Surprise Down Error Status Data Link Protocol Error Status Undefined 22 21 20 19 26 25 24 23 18 17 16 15 14 13 12 11 6 5 4 3 1 0 31 Figure 9 2 Correctable Error Status Register The default value of all the bits of this register is 0 An error status bit that is set indicates that the error condition it represents has been detected Software may clear the error st...

Page 126: ...cal Layer initializes the speed lane numbering and lane width of the PCI Express link according to packets received from the link and directives received from higher layers The following figure provides a high level block diagram 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and r...

Page 127: ...ck Configuration Space PCS PMA Physical Layer Transceivers Configuration via PCIe Link CvP RX Buffer PHY IP Core for PCI Express PIPE Avalon MM DMA Bridge Table 10 1 Application Layer Clock Frequencies Lanes Gen1 Gen2 Gen3 2 N A N A 125 MHz 128 bits 4 N A 125 MHz 128 bits 250 MHz 128 bits or 125 MHz 256 bits 8 125 MHz 128 bits 250 MHz 128 bits or 125 MHz 256 bits 250 MHz 256 bits Related Informati...

Page 128: ...of the device is initialized Interrupts The Hard IP for PCI Express offers the following interrupt mechanisms Message Signaled Interrupts MSI MSI uses the Transaction Layer s request acknowledge handshaking protocol to implement interrupts The MSI Capability structure is stored in the Configu ration Space and is programmable using Configuration Space accesses MSI X The Transaction Layer generates ...

Page 129: ...component communication by TLP transmission in the interconnect fabric The DLL implements the following functions Link management through the reception and transmission of DLL packets DLLP which are used for the following functions Power management of DLLP reception and transmission To transmit and receive ACK NACK packets Data integrity through generation and checking of CRCs for TLPs and DLLPs T...

Page 130: ...atus to the Configuration Space Power Management This function handles the handshake to enter low power mode Such a transition is based on register values in the Configuration Space and received Power Management PM DLLPs Data Link Layer Packet Generator and Checker This block is associated with the DLLP s 16 bit CRC and maintains the integrity of transmitted packets Transaction Layer Packet Genera...

Page 131: ...s and transmits packets across a link and accepts and decodes received packets The Physical Layer connects to the link through a high speed SERDES interface running at 2 5 Gbps for Gen1 implementations at 2 5 or 5 0 Gbps for Gen2 implementations and at 2 5 5 0 or 8 0 Gbps for Gen3 implementations The Physical Layer is responsible for the following actions Initializing the link Scrambling descrambl...

Page 132: ...er To Link To Data Link Layer The Physical Layer is subdivided by the PIPE Interface Specification into two layers bracketed horizon tally in above figure Media Access Controller MAC Layer The MAC layer includes the LTSSM and the scrambling descrambling and multilane deskew functions PHY Layer The PHY layer includes the 8B 10B and 128b 130b encode decode functions elastic buffering and serializati...

Page 133: ...t and interacts with the TX alignment block to prevent the insertion of a SKP Ordered Set in the middle of packet Deskew This sub block performs the multilane deskew function and the RX alignment between the number of initialized lanes and the 64 bit data path The multilane deskew implements an eight word FIFO buffer for each lane to store symbols Each symbol includes eight data bits one disparity...

Page 134: ...criptor simplifies the design Altera recommends that you embed the DMA Descriptor Controller in the Avalon MM DMA bridge if you do not plan to modify it Refer to Getting Started with the Arria 10 Avalon MM DMA for an example that includes the embedded DMA Descriptor Controller Figure 10 4 Avalon MM DMA Block Diagram with Embedded DMA Descriptor Controller PCIe Avalon MM DMA Bridge Hard IP for PCIe...

Page 135: ...096 bytes which is the maximum allowed by the PCI Express specification If you plan to modify or replace the DMA Descriptor Controller Altera recommends that you instantiate it separately The following block diagram illustrates this configuration Your descriptor controller must interface to the DMA read and DMA write modules that are always part of the PCI Express Avalon MM DMA bridge You may need...

Page 136: ... it in the local FIFO It then fetches the table entries and directs the DMA to transfer the data between the Avalon and PCIe domains one descriptor at a time It also sends DMA status upstream via the TX slave port For more information about the Descriptor Control module registers refer to DMA Descriptor Controller Registers on page 7 15 RX Master You can select either a single dword or high perfor...

Page 137: ...id Link Training Issues Successful link training can only occur after the FPGA is configured Designs using CvP for configuration initially load the I O ring and periphery image Arria 10 devices include a Nios II Hard Calibration IP core that automatically calibrates transceivers to optimize signal quality after CvP completes and before 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLO...

Page 138: ... Information Arria 10 Transceiver PHY User Guide For information about requirements for the CLKUSR pin used during automatic calibration SDC Timing Constraints Your top level Synopsys Design Constraints file sdc must include the following timing constraint macro for the Arria 10 Hard IP for PCIe IP core Example 11 1 SDC Timing Constraints Required for the Arria 10 Hard IP for PCIe and Design Examp...

Page 139: ...s and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s ...

Page 140: ... Write Status and Descriptor Base Low registers 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holde...

Page 141: ... the AVMM interface parameter in Interface System Settings This parameter is available in the IP core v15 0 and later 2015 05 04 15 0 Added Enable Altera Debug Master Endpoint ADME parameter to support optional Native PHY register programming with the Altera System Console Added support for downstream burst read request for a payload of size up to 4 KB if Enable burst capability for RXM BAR2 port ...

Page 142: ... Arria 10 Avalon MM DMA for PCI Express IP core Revised programming model for the Descriptor Controller Added simulation log file altpcie_monitor_a10_dlhip_tlp_file_log log that is automatically generated in your simulation directory To simulate in the Quartus II 14 0 software release you must regenerate your IP core to create the supporting monitor file that generates altpcie_monitor_a10_dlhip_tl...

Page 143: ...d definition of Device ID and Sub system Vendor ID to say that these registers are only valid in the Type 0 Endpoint Configuration Space Removed 125 MHz clock as optional refclk frequency in Arria 10 devices Arria 10 devices support an 100 MHz reference clock as specified by the PCI Express Base Specification Rev 3 0 Added Next Steps in Creating a Design for PCI Express to Datasheet chapter Remove...

Page 144: ...e final descriptor completes Removed the following chapters that have minimal relevance to the Arria 10 Avalon MM DMA Interface IP Core These chapters are available in the more comprehensive Avalon ST versions Design Implementation Optional Features Debugging Throughput Optimization 2013 12 02 13 1 Arria 10 Initial release How to Contact Altera To locate the most up to date information about Alter...

Page 145: ...e Save As dialog box For GUI elements capitaliza tion matches the GUI bold type Indicates directory names project names disk drive names file names file name extensions software utility names and GUI labels For example qdesigns directory D drive and chiptrip gdf file Italic Type with Initial Capital Letters Indicate document titles For example Stratix IV Design Guidelines italic type Indicates var...

Page 146: ...ou to press the Enter key 1 2 3 anda b c and so on Numbered steps indicate a list of items when the sequence of the items is important such as the steps listed in a procedure Bullets indicate a list of items when the sequence of the items is not important 1 The hand points to information that requires special attention h The question mark directs you to a software help system with related informat...

Page 147: ...ate notifications for Altera documents The Feedback icon allows you to submit feedback to Altera about the document Methods for collecting feedback vary as appropriate for each document Related Information Email Subscription Management Center B 8 Typographic Conventions UG 01145_avmm_dma 2015 11 02 Altera Corporation Additional Information Send Feedback ...

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