Alphi CPCI-QIPC, Reference Manual

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CPCI-QIPC REFERENCE MANUAL
ALPHI TECHNOLOGY CORP. Page 9 Ver 1.1
Part Number :
739-11-000-4000
Copyright ALPHI Technology Corporation ,1998
at 3 or more wait states of the C31, with more when the HOST is accessing it as well. The
HOST has priority during arbitration for a given cycle.
3.4 IP INTERFACE and PAGED MEMORY
The ID and IO space for the IPs are directly accessed based on the memory map below. IP
memory space is overlaid with the EPROM and FLASH space, and is controlled via the
register CTRL 1.
3.5 DSP MEMORY AND REGISTER MAP SUMMARY
NAME START END DATA R/W COMMENTS
SRAM $000000 $01FFFF D00-D31 R/W Zero wait state static RAM
EPROM $400000 $47FFFF D00-D07 R/W 512K x 8
FLASH $480000 $49FFFF D00-D07 R/W Software write protected
IPMEMSL_A $400000 $7FFFFF D00-D15 R/W IP_A memory ( 8 Mbytes )
IPMEMSL_B $400000 $7FFFFF D00-D15 R/W IP_B memory ( 8 Mbytes )
IPMEMSL_C $400000 $7FFFFF D00-D15 R/W IP_C memory ( 8 Mbytes )
IPMEMSL_D $400000 $7FFFFF D00-D15 R/W IP_D memory ( 8 Mbytes )
DP_SRAM $B00000 $BFFFFF D00-D31 R/W Dual Port SRAM (4Mbytes)
CTRL1 $F00000 $F00000 D01-D03 W Controls internal settings
CTRL2 $F00002 $F00002 D01-D03 W Controls internal settings
C31_STAT1 $F00008 $F00008 D00-D07 R IP interrupt status
C31_STAT2 $F00009 $F00009 D00-D07 R IP DMA status
C31_STAT3 $F0000A $F0000A D00-D07 R Miscellaneous status
BERR_RST $F00028 $F00028 D00-D07 W Reset Bus Error Status
IPSTROBE $F00038 $F00038 D00-D31 W Assert *IPSTROBE
SCC8530 $F00040 $F00043 D00-D07 R/W Serial communication port
AMCC $F00080 $F000FF D00-D31 R/W AMCC REGISTERS
IDSEL_A $F00400 $F0043F D00-D15 R/W IP_A ID Space
INTGNT_A $F00440 $F0047F D00-D07 R Interrupt vector from IP_A
IOSEL_A $F00480 $F004BF D00-D15 R/W IP_A I/O Space
IDSEL_B $F00500 $F0053F D00-D15 R/W IP_B ID Space
INTGNT_B $F00540 $F0057F D00-D07 R Interrupt vector from IP_B
IOSEL_B $F00580 $F005BF D00-D15 R/W IP_B I/O Space
IDSEL_C $F00600 $F0063F D00-D15 R/W IP_C ID Space
INTGNT_C $F00640 $F0067F D00-D07 R Interrupt vector from IP_C
IOSEL_C $F00680 $F006BF D00-D15 R/W IP_C I/O Space
IDSEL_D $F00700 $F0073F D00-D15 R/W IP_D ID Space
INTGNT_D $F00740 $F0077F D00-D07 R Interrupt vector from IP_D
IOSEL_D $F00780 $F007BF D00-D15 R/W IP_D I/O Space
Table 3.2: DSP Memory Map