Alphi CPCI-QIPC, Reference Manual

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CPCI-QIPC REFERENCE MANUAL
ALPHI TECHNOLOGY CORP. Page 11 Ver 1.1
Part Number :
739-11-000-4000
Copyright ALPHI Technology Corporation ,1998
To prevent this from happening, and hanging the DSP, any access to an IP also starts a
timer to ensure that the cycle completes. The fact that a cycle has timed out has occurred is
reported in C31_STAT3, and can be cleared by writing to BERR_RST.
If this bit is set, an IP interrupt is generated. Otherwise, no interrupt is generated.
3.5.3 C31_STAT1 INTERRUPT STATUS REGISTER (Read Only)
BIT 07 BIT 06 BIT 05 BIT 04 BIT 03 BIT 02 BIT 01 BIT 00
IP_D
IREQ1 IP_D
IREQ0 IP_C
IREQ1 IP_C
IREQ0 IP_B
IREQ1 IP_B
IREQ0 IP_A
IREQ1 IP_A
IREQ0
Each IP module can generate two different interrupts. When any Industry Pack generates
an interrupt, the corresponding interrupt is ORed with other pending interrupts. The DSP
can read this register to determine which interrupts are pending.
3.5.4 C31_STAT2 DMA STATUS REGISTER (Read Only)
BIT 07 BIT 06 BIT 05 BIT 04 BIT 03 BIT 02 BIT 01 BIT 00
IP_D
DMA1 IP_D
DMA0 IP_C
DMA1 IP_C
DMA0 IP_B
DMA1 IP_B
DMA0 IP_A
DMA1 IP_A
DMA0
The Industry Pack Specification allows for the possibility for an IP to request a DMA
transfer. The
CPCI-QIPC does not directly support this option. However it is possible for the
DSP to recognize a DMA request by polling the C31 STAT2 register. There is no interrupt
support or direct DMA support by the DSP.
3.5.5 C31_STAT3 MISCELLANEOUS STATUS REGISTER (Read Only)
BIT 07 BIT 06 BIT 05 BIT 04 BIT 03 BIT 02 BIT 01 BIT 00
Jumper
W7 Jumper
W8 CBERR
CBERR Bus Error Status
The DSP C31 can read this status register to know that a access to an IP has not
responded by asserting *IPACK. This status is reset with a write to BERR_RST.
JUMPER W3, W5 Status of Hardware Jumpers
These hardware jumpers are available for the use of the customer. If the jumper is installed,
the bit reads as a 0.
3.5.6 BERR_RST (Write Strobe Only)
A write to this location will reset the CBERR bit in the C31_STAT3 register.
3.5.7 IPSTROBE (Write Strobe Only)
If the CTRL2 Register is configured to allow it, a write to this location will trigger a pulse on
the *IPSTROBE line to all the IPs.