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CPCI-QIPC  REFERENCE MANUAL

ALPHI TECHNOLOGY CORP.

Page 18 

Ver 1.1

Part Number : 

739-11-000-4000

 Copyright ALPHI Technology Corporation ,1998

IP I/O Line

Header and Pin

Header and Pin

Backplane and Pin

IP_B:1

H15:19

H15:20

J4:25

IP_B:2

H14:19

H14:20

J4:50

IP_B:3

H13:19

H13:20

J4:75

IP_B:4

H12:19

H12:20

J4:100

IP_B:5

H11:19

H11:20

J4:125

IP_B:6

H15:17

H15:18

J4:24

IP_B:7

H14:17

H14:18

J4:49

IP_B:8

H13:17

H13:18

J4:74

IP_B:9

H12:17

H12:18

J4:99

IP_B:10

H11:17

H11:18

J4:124

IP_B:11

H15:15

H15:16

J4:23

IP_B:12

H14:15

H14:16

J4:48

IP_B:13

H13:15

H13:16

J4:73

IP_B:14

H12:15

H12:16

J4:98

IP_B:15

H11:15

H11:16

J4:123

IP_B:16

H15:13

H15:14

J4:22

IP_B:17

H14:13

H14:14

J4:47

IP_B:18

H13:13

H13:14

J4:72

IP_B:19

H12:13

H12:14

J4:97

IP_B:20

H11:13

H11:14

J4:122

IP_B:21

H15:11

H15:12

J4:21

IP_B:22

H14:11

H14:12

J4:46

IP_B:23

H13:11

H13:12

J4:71

IP_B:24

H12:11

H12:12

J4:96

IP_B:25

H11:11

H11:12

J4:121

IP_B:26

H15:9

H15:10

J4:20

IP_B:27

H14:9

H14:10

J4:45

IP_B:28

H13:9

H13:10

J4:70

IP_B:29

H12:9

H12:10

J4:95

IP_B:30

H11:9

H11:10

J4:120

IP_B:31

H15:7

H15:8

J4:19

IP_B:32

H14:7

H14:8

J4:44

IP_B:33

H13:7

H13:8

J4:69

IP_B:34

H12:7

H12:8

J4:94

IP_B:35

H11:7

H11:8

J4:119

IP_B:36

H15:5

H15:6

J4:18

IP_B:37

H14:5

H14:6

J4:43

IP_B:38

H13:5

H13:6

J4:68

IP_B:39

H12:5

H12:6

J4:93

IP_B:40

H11:5

H11:6

J4:118

IP_B:41

H15:3

H15:4

J4:17

IP_B:42

H14:3

H14:4

J4:42

IP_B:43

H13:3

H13:4

J4:67

IP_B:44

H12:3

H12:4

J4:92

IP_B:45

H11:3

H11:4

J4:117

IP_B:46

H15:1

H15:2

J4:16

IP_B:47

H14:1

H14:2

J4:41

IP_B:48

H13:1

H13:2

J4:66

IP_B:49

H12:1

H12:2

J4:91

IP_B:50

H11:1

H11:2

J4:116

Summary of Contents for CPCI-QIPC

Page 1: ...CI systems Up to Four IndustryPack Modules Dual Ported SRAM between CPCI and DSP C31 REFERENCE MANUAL 739 11 000 4000 Version 1 1 May 1998 ALPHI TECHNOLOGY CORPORATION 6202 S Maple Avenue 120 Tempe AZ...

Page 2: ...s manual or from the use of information contain herein ALPHI TECHNOLOGY reserves the right to make any changes without notice to this or any of ALPHI TECHNOLOGY s products to improve reliability perfo...

Page 3: ...________________________ 9 3 5 DSP MEMORY AND REGISTER MAP SUMMARY________________________________ 9 3 6 RESET SIGNALS ________________________________________________________ 12 3 7 LOCAL DSP INTERRU...

Page 4: ...nt in Figure 1 3 The CPCI QIPC can operate as a slave that is managed by the host processor on the CPCI bus or it can operate in a standalone mode of operation without a host The IP modules share a co...

Page 5: ...CI to Local Bus Bridge Mailbox Registers DSP C31 32 MHz Local SRAM 128K x 32 Local FLASH 128K x 8 or 512K x 8 Local EPROM Boot 512K x 8 IP A IP B IP D IP C Dual Ported SRAM 1M x 32 Dual Port Arbitrati...

Page 6: ...MANUAL ALPHI TECHNOLOGY CORP Page 3 Ver 1 1 Part Number 739 11 000 4000 Copyright ALPHI Technology Corporation 1998 IP A IP C IP B IP D W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W13 W12 W14 W16 W15 Figure 1...

Page 7: ...t Number 739 11 000 4000 Copyright ALPHI Technology Corporation 1998 P1 P2 IP A IP C IP B IP D P6 P5 P4 P3 J1 J5 J4 H 5 H 1 H 2 H 3 H 4 H 1 0 H 6 H 7 H 8 H 9 H 1 5 H 1 1 H 1 2 H 1 3 H 1 4 H 2 0 H 1 6...

Page 8: ...able from the following source PCI Special Interest Group PO Box 14070 Portland OR 97214 Tel 800 433 5177 Tel 503 797 4207 Fax 503 234 6762 The reader is also referred to the S5933 PCI Controller data...

Page 9: ...ns from the CPCI system after RESET based on the values stored in the NVRAM device read by the AMCC PCI interface chip The decode addresses of these regions are assigned by the host processor The CPCI...

Page 10: ...Control Status Register 0x3C MCSR Bus Master Control Status Register Table 2 2 AMCC Registers HOST For more information about these registers refer to the AMCC PCI controller manual 3 C31 SIDE 3 1 IN...

Page 11: ...ilboxes are shown below in Table 3 1 3 2 3 ADDITIONAL REGISTERS The AMCC S5933 PCI controller has a set of additional registers to control and monitor the behavior of the CPCI interface The address of...

Page 12: ...FFF D00 D31 R W Dual Port SRAM 4Mbytes CTRL1 F00000 F00000 D01 D03 W Controls internal settings CTRL2 F00002 F00002 D01 D03 W Controls internal settings C31_STAT1 F00008 F00008 D00 D07 R IP interrupt...

Page 13: ...lt setting This bit must be set to a one when using a double width IP Note that the DSP always reads or writes in 32 bits however only the lower 16 bits are valid when 32BIT_AB 0 3 5 2 CTRL2 Write Onl...

Page 14: ...BIT 04 BIT 03 BIT 02 BIT 01 BIT 00 IP_D DMA1 IP_D DMA0 IP_C DMA1 IP_C DMA0 IP_B DMA1 IP_B DMA0 IP_A DMA1 IP_A DMA0 The Industry Pack Specification allows for the possibility for an IP to request a DM...

Page 15: ...cations including HDLC SDLC and multidrop configurations Clocking can be provided externally or internally 3 6 RESET SIGNALS The CPCI QIPC can be reset from two different sources At power on the watch...

Page 16: ...oftware configuration The state is available in C31_STAT3 W8 None Available to user for software configuration The state is available in C31_STAT3 W9 None When shorted provides DSP and IP reset W10 No...

Page 17: ...ECTORS 50 pin subminiature D shelled connectors are used to route all the IP I O signals off the card ALPHI Technology can supply transition modules and cable assemblies to meet any special requiremen...

Page 18: ...ound 6 Request To Send 7 Ground 8 No Connection 9 No Connection Table 6 3 Serial RS232 Port P4 1 5 6 9 Figure 6 2 Serial RS232 Port P4 6 3 SERIAL RS422 RS485 PORT P3 Port B of the 8530 is configured a...

Page 19: ...X0 3 FSR0 4 FSX0 5 Ground 6 Ground 7 DR0 8 DX0 9 DR0 10 DX0 11 Ground 12 Ground 13 CLKR0 14 CLKX0 15 CLKR0 16 CLKX0 Table 6 5 DSP Serial Port P15 6 5 EMULATOR CONNECTION P17 This connector is used to...

Page 20: ...H18 13 H18 14 J4 58 IP_A 19 H17 13 H17 14 J4 83 IP_A 20 H16 13 H16 14 J4 108 IP_A 21 H20 11 H20 12 J4 7 IP_A 22 H19 11 H19 12 J4 32 IP_A 23 H18 11 H18 12 J4 57 IP_A 24 H17 11 H17 12 J4 82 IP_A 25 H16...

Page 21: ...13 13 H13 14 J4 72 IP_B 19 H12 13 H12 14 J4 97 IP_B 20 H11 13 H11 14 J4 122 IP_B 21 H15 11 H15 12 J4 21 IP_B 22 H14 11 H14 12 J4 46 IP_B 23 H13 11 H13 12 J4 71 IP_B 24 H12 11 H12 12 J4 96 IP_B 25 H11...

Page 22: ...14 J5 30 IP_C 18 H8 13 H8 14 J5 52 IP_C 19 H7 13 H7 14 J5 74 IP_C 20 H6 13 H6 14 J5 96 IP_C 21 H10 11 H10 12 J5 7 IP_C 22 H9 11 H9 12 J5 29 IP_C 23 H8 11 H8 12 J5 51 IP_C 24 H7 11 H7 12 J5 73 IP_C 25...

Page 23: ...J5 41 IP_D 18 H3 13 H3 14 J5 63 IP_D 19 H2 13 H2 14 J5 85 IP_D 20 H1 13 H1 14 J5 107 IP_D 21 H5 11 H5 12 J5 18 IP_D 22 H4 11 H4 12 J5 40 IP_D 23 H3 11 H3 12 J5 62 IP_D 24 H2 11 H2 12 J5 84 IP_D 25 H1...

Page 24: ...oved or they will interfere with the correct operation of the PCI host When the board is operated in stand alone mode the board can by operated under an emulator and by downloading and executing progr...

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