CPCI-QIPC REFERENCE MANUAL
ALPHI TECHNOLOGY CORP.
Page 10
Ver 1.1
Part Number :
739-11-000-4000
Copyright ALPHI Technology Corporation ,1998
3.5.1 CTRL1 (Write Only)
BIT 07
BIT 06
BIT 05
BIT 04
BIT 03
BIT 02
BIT 01
BIT 00
BANKSEL1
BANKSEL0
32BIT_AB
FLASH
FLASH, BANKSEL0, BANKSEL1
Memory Page Selection
The FLASH and EPROM, and the four IP memory spaces are all paged into a common DSP
address range starting at 0x400000. Selection of the appropriate page is accomplished by
programming the FLASH, BANKSEL0, and BANKSEL1 bits.
CTRL1
Page Selection
0x0
FLASH and EPROM (default)
0x1
IP_A Memory Space
0x5
IP_B Memory Space
0x9
IP_C Memory Space
0xD
IP_D Memory Space
Table 3-3: Memory Page Selection
32BIT_AB
32-bit Width Enable
Setting this bit to a one enables the IP interface A and B for 32-bit transfers. Setting this bit
to a zero disables the 32-bit transfers (default setting). This bit must be set to a one when
using a double width IP. Note that the DSP always reads or writes in 32-bits, however only
the lower 16 bits are valid when 32BIT_AB = 0.
3.5.2 CTRL2 (Write Only)
BIT 07
BIT 06
BIT 05
BIT 04
BIT 03
BIT 02
BIT 01
BIT 00
EXTRIG_EN
CBERR_EN 32BIT_CD
TCLK1_EN
TCLK1_EN, EXTRIG_EN
Signal routing to IPSTROBE
See the following table for routing signals to *IPSTROBE.
TCLK1_EN,
EXTRIG_EN
Result
0
0
Connect DSP Timer 1 output to *IPSTROBE
1
0
Software writes to register IPSTROBE (0xF00038) output to
*IPSTROBE
X
1
External TTL trigger on W13 output to *IPSTROBE
32BIT_CD
32-bit Width Enable
Setting this bit to a one enables the IP interface C and D for 32-bit transfers. Setting this bit
to a zero disables the 32-bit transfers (default setting). This bit must be set to a one when
using a double width IP. Note that the DSP always reads or writes in 32-bits, however only
the lower 16 bits are valid when 32BIT_CD = 0.
CBERR_EN
Local Bus Error enable
Any access to a non-existent IP will never complete since no device will assert *IPACK.
