CPCI-QIPC REFERENCE MANUAL
ALPHI TECHNOLOGY CORP.
Page 12
Ver 1.1
Part Number :
739-11-000-4000
Copyright ALPHI Technology Corporation ,1998
3.5.8 SERIAL PORT (Read / Write)
The DSP processor on the
CPCI-QIPC
has access to a SCC85C30 serial communication
controller. The 8530 provides an RS232C asynchronous serial communication port and an
RS422 port.
The bootloader and hardware support libraries supplied with the
CPCI-QIPC
utilizes the
RS232C port for a console for standard input and output by the DSP. The customer may
alternatively wish to write his own software to use this port. Examples are provided in the
Board Support Package
.
There is hardware support for many RS422 and RS485 applications including HDLC,
SDLC, and multidrop configurations. Clocking can be provided externally or internally.
3.6 RESET SIGNALS
The
CPCI-QIPC
can be reset from two different sources:
•
At power on, the watchdog timer will hold the C31 RESET line and the IP reset lines low
for 200 ms.
•
The AMCC has a bit called SYSRST which the HOST can toggle to reset the DSP and
IP resets. Software should hold the RESET asserted for 200 mS to meet the IP
specifications
3.7 LOCAL DSP INTERRUPT SOURCES
The local DSP has four interrupt lines. The source of each interrupt is listed in the table
below. Additionally, at reset, the INT1 line is pulsed to tell the C31 to find the EPROM
image at 0x400000 (if boot mode is MC).
SOURCE
ENABLE SIGNAL
INTERRUPT LEVEL
SCC8530
Inside SCC8530
INT0
Bus Error
CBERR_EN
INT0
AMCC
Inside 5933
INT1
AMCC FIFO:
WR not Full
RD not Empty
None
INT2
IP interrupt
None
INT3
Table 3-4
