CPCI-QIPC REFERENCE MANUAL
ALPHI TECHNOLOGY CORP.
Page 16
Ver 1.1
Part Number :
739-11-000-4000
Copyright ALPHI Technology Corporation ,1998
6.4 DSP SERIAL PORT (P15)
The serial shift register of the DSP is also available for use as desired by the customer. The
input and outputs are connected to 55194 and 55195 bipolar line drivers and receivers as
shown in the following table. The signals are output off the board through a 2x8 100 mil
header. See the DSP Processor manual for details on how to use the serial port.
Pin
Description
Pin
Description
1
FSR0 -
2
FSX0 +
3
FSR0 +
4
FSX0 -
5
Ground
6
Ground
7
DR0 -
8
DX0 +
9
DR0 +
10
DX0 -
11
Ground
12
Ground
13
CLKR0 -
14
CLKX0 +
15
CLKR0 +
16
CLKX0 -
Table 6.5: DSP Serial Port (P15)
6.5 EMULATOR CONNECTION (P17)
This connector is used to connect the emulator to the C31 DSP. It follows the standard form
as described by TI in their processor manual.
6.6 32 BIT CPCI BUS (J1)
This connector plugs into the backplane and provides the standard CPCI signals for all
CPCI systems.
6.7 Backplane I/O Connections (J4 and J5)
The board is designed to optionally output the I/O lines from the IPs out the back panel if
desired by the customer. By installing jumper blocks on the 20 headers H1 – H20, the IP I/O
lines are connected to J4 and J5. Alternatively, the customer can wirewrap a custom pinout
if desired.
