CPCI-QIPC REFERENCE MANUAL
ALPHI TECHNOLOGY CORP.
Page 7
Ver 1.1
Part Number :
739-11-000-4000
Copyright ALPHI Technology Corporation ,1998
AMCC chip or to the Dual Port SRAM. The PCI Operation Registers of the AMCC 5933 chip
are depicted below:
Offset
Register Name
0x00
OMB1 Outgoing Mailbox Register 1
0x04
OMB2 Outgoing Mailbox Register 2
0x08
OMB3 Outgoing Mailbox Register 3
0x0C
OMB4 Outgoing Mailbox Register 4
0x10
IMB1 Incoming Mailbox Register 1
0x14
IMB2 Incoming Mailbox Register 2
0x18
IMB3 Incoming Mailbox Register 3
0x1C
IMB4 Incoming Mailbox Register 4
0x20
FIFO Register Port (bi-directional)
0x24
MWAR Master Write Address Register
0x28
MWTC Master Write Transfer Counter
0x2C
MRAR Master Read Address Register
0x30
MRTC Master Read Transfer Counter
0x34
MBEF Mailbox Empty/Full Status
0x38
INTCSR Interrupt Control/Status Register
0x3C
MCSR Bus Master Control/Status Register
Table 2.2: AMCC Registers (HOST)
For more information about these registers refer to the AMCC PCI controller manual.
3.
C31 SIDE
3.1 INTERNAL ORGANIZATION
The
CPCI-QIPC
card is divided into different sections. Each section and its relationship to
other sections will be discussed. The
CPCI-QIPC
sections are:
•
CPCI interface
•
Dual Port Memory
•
IP interface
3.2 CPCI INTERFACE
The local DSP processor communicates with the CPCI bus through the AMCCS9533 chip
that provides bi-directional FIFO and Mailbox registers. The
CPCI-QIPC
can function as
both a servant (CPCI target) or as a master (CPCI initiator) for DMA access. The following
interface descriptions refer to the CPCI interface as seen by the local DSP. The AMCC
registers are located at DSP address 0xf00080.
3.2.1 BI-DIRECTIONAL FIFO
Two separate FIFO data paths are implemented within the AMCCS9533, a read FIFO that
allows data transfers from the module to the CPCI bus and a write FIFO that transfers data
