Akai PDP42Z5TA - 42" Plasma TV, Service Manual

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CE2836
CREGA, Chip Control Register (
ADRS
=hex0A, default=hex00)
DAMSTR: Configure the DAC PCM Serial Port.
0: - Slave Mode
1: - Master Mode.
DAPWD:
DAC Power Down
0: DAC enabled
1: DAC Power Down.
ADMSTR: Configure the ADC PCM Serial Port.
0: - Slave Mode
1: - Master Mode.
ADPWD:
ADC Power Down
0: ADC enabled
1: ADC Power Down.
ZCBYP:
Disable ADC Zero Crossing Detection
0: Zero crossing is enabled.
1: Zero crossing is bypassed.
HPFBYP: Bypass ADC data path High Pass Filter
0: Enable high pass filter.
1: Disable high pass filter.
ADDR[3:0]
CREG1[7:0]
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Hex 0A
DAMSTR
DAPWD X X ADMSTR ADPWD ZCBYP HPFBYP
Default Value 0 0 0 0 0 0 0 0
82／148