CE2836
CREG 8, ADC Proc Register (
ADRS
=hex08, default=hex82)
NGATE: Noise Gate
0: - Noise Gate Disabled.
1: -Noise Gate Enable. When the signal level is lower than the level specified by the NGTH the ADC output
will be zeroed.
NGTH[1:0]: - Specified the Noise Gate Threshold.
00: - -66dB
01: - -72 dB.
10: - -78dB.
11: - -84 dB.
ALCHTM: - Automatic Level Control Hold time.
0: - 340 ms. (default). For music program.
1: - 5.3 ms. This should be used for speech conversion.
ALCEN: - Enable Automatic Level Control Function
0: - Disable ALC. (default)
1: - Enable ALC.
ALC[2:0]: - ALC Target Level.
000: - -1 dB.
001: - -2 dB.
010: - -3 dB. (default)
011: - -4 dB.
100: - -5 dB.
101: - -6 dB.
110: - -7 dB.
111: - -8 dB.
ADDR[3:0]
CREG0[7:0]
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Hex 08
NGATE
NGTH[1:0]
ALCHTM
ALCEN
ALC[2:0]
Default Value
1
0
0
0
0
0
1
0
80/148
Summary of Contents for PDP42Z5TA - 42" Plasma TV
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Page 101: ...Product Specification of 42XGA PDP Module Specification For Approval 99 148...
Page 117: ...Product Specification of 42XGA PDP Module 115 148...
Page 129: ...Product Specification of 42XGA PDP Module Confidential 6 OUTLINE DRAWING Front View 127 148...
Page 130: ...Product Specification of 42XGA PDP Module Rear View 128 148...
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