Akai PDP42Z5TA - 42" Plasma TV, Service Manual

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CE2836
CREG9, ADC Control Register (
ADRS
=hex09, default=hexA0)
MT[1:0] Digital Serial Bus Format Select for ADC.
00: - Normal or Right Justified Format.
01: -Left Justified Format.
10: - I2S Format.(default)
11: - TDM, Multi-channel Time Division Multiplex Format
NBIT[1:0]: - These two bits define the ADC serial audio input resolution for right justified and TDM mode
00: - 16-bit resolution.
01: - 20-bit resolution.
10: - 24-bit resolution (default).
11: - 32-bit resolution.
SRC[1:0]: - ADC Sampling Rate Selection. It is used in the ADC Master Mode, CRA[1]==1, to generate ADFS and
ADBCK.
00: - Sampling Rate = XCK/256.
01: - Sampling Rate = XCK/128.
10: - Sampling Rate = XCK/384.
11: - Sampling Rate = XCK/192.
CKDIV2: - Enable the ADXCK Clock divided by 2.
0: - ADC system clock is ADXCK (default)
1: - ADC system clock is ADXCK/2
ADDR[3:0]
CREG0[7:0]
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Hex 09 FMT[1:0] NBIT[1:0] X SRC[1:0] CKDIV2
Default Value 1 0 1 0 0 0 0 0
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