CE2836
DIN3
3
I
DAC Channel 3 serial audio data input.
DOUT
4
O
Serial ADC output
VDD
5
+3.3V
Digital power supply, 3.3 Volt.
GND
6
GND
Digital ground
ADFS
7
I/O
ADC left/right channel clock pin. Please refer to Figure 1 PCM data format for its
definition.
Input (default) if ADC I/F is configured to be
‘slave’
else it is an output
ADBCK
8
I/O
External master clock input for ADC.
Input (default) if ADC I/F is configured to be
‘slave’
else it is an output
ADXCK
9
I
ADC audio serial data clock input.
GND
10
I
Digital ground
Analog
N/C
11
No connection. It can be tied to AGND.
AINR5
12
I
ADC channel 5 right input. Input resistance is 20K Ohm
AINL5
13
I
ADC channel 5 left input. Input resistance is 20K Ohm
N/C
14
No connection. It can be tied to AGND.
AINR4
15
I
ADC channel 4 right input. Input resistance is 20K Ohm
AINL4
16
I
ADC channel 4 left input. Input resistance is 20K Ohm
AINR3
17
I
ADC channel 3 right input. Input resistance is 20K Ohm
AINL3
18
I
ADC channel 3 left input. Input resistance is 20K Ohm
AINR2
19
I
ADC channel 2 right input. Input resistance is 20K Ohm
AINL2
20
I
ADC channel 2 left input. Input resistance is 20K Ohm
AINR1
21
I
ADC channel 1 right input. Input resistance is 20K Ohm
AINL1
22
I
ADC channel 1 left input. Input resistance is 20K Ohm
AVDD
23
+3.3V
ADC power supply.
N/C
24
No connection. It can be tied to AGND.
AGND
25
GND
Analog ground pin.
ADVRF
26
O
ADC reference voltage. It should be decoupled to AGND with a 22 uF capacitor in
parallel with a 0.1 uF. Its value should be AVDD/2 volt.
AGND
27
GND
Analog ground pin.
PIN DESCRIPTION (Continued)
Pin Name
Pin #
Type
Description
70/148
Summary of Contents for PDP42Z5TA - 42" Plasma TV
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