Akai PDP42Z5TA - 42" Plasma TV, Service Manual

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Product Specification of 42XGA PDP Module
‰
LVDS Signal (continued)
¾
Signal Input sequence of LVDS Receiver
RxCLK IN
(Differential)
RD
RC
RB
RA
Previous cycle Next cycle
NC B3 B2 G3 G2 R3 R2
DE VS HS B9 B8 B7 B6
B5 B4 G9 G8 G7 G6 G5
G4 R9 R8 R7 R6 R5 R4
R3-1 R2-1
B7-1 B6-1
G6-1 G5-1
R5-1 R4-1
RE
NC B1 B0 G1 G0 R1 R0 R1-1 R0-1
※
DE : BLANK, VS : Vsync, HS : Hsync
※
To use (only) 8bit video signal, “TE+” is to be tied to ground signal and
“TE-” is to be tied to 3.3V signal. (to set the 2 LSB of 10 bits video signal to ‘0’)
¾
8bit application
¾
10bit application
twisted
pair cable
LVDS Con
n
ector (Tx)
LVDS Con
n
ector (Rx)
LVDS
Transmitte
r
(10 bits)
TA+/-
TB+/-
TC+/-
TD+/-
LVDS
R
eceiv
er
(10 bits)
RA+/-
RB+/-
RC+/-
RD+/-
RE+/-
PDP module side
Video Board Side
(VSC)
TE+/-
☞
Default 8 bit input ( For 10 bit input, it need to discuss with PDP Division )
TE+
twisted
pair cable
LVDS Con
n
ector (Tx)
LVDS Con
n
ector (Rx)
LVDS
Transmitte
r
(8 bits)
TA+/-
TB+/-
TC+/-
TD+/-
LVDS
R
eceiv
er
(10 bits)
RA+/-
RB+/-
RC+/-
RD+/-
RE+/-
3.3V
GND
TE-
PDP module side
Video Board Side
(VSC)
111／148