Akai PDP42Z5TA - 42" Plasma TV, Service Manual

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CE2836
ADC Noise Gate
Noise Gate remove hissing noise during silence period. It is useful for recording noisy program. While Noise Gate is enabled
the ADC digital output will be zeroed if the signal level below a predetermined value for about 0.5 seconds. The noise Gate is
controlled by the same ADC PROC. REGISTER.
Serial Command Port
The user can select the chip operation mode by programming the internal control registers through serial I
2
C port. The Chip
Address for the CE2836 is 35H. The protocol for write operation consists of sending 3 byte data to CE2836, following each
byte is the acknowledges generated by CE2836. The first byte is the 7-bit Chip Address followed by the read/write bit (read is
high, write is low). The second byte is the control register address. The third byte is the control register data.
Upon power up, all programmable registers are set to default values. Figure 2 describes the serial command port timing
relationship.
Figure 2. Serial Command Port Timing
Table (7): Noise Gate Threshold
NGTH[1:0] Threshold
00 -66 dB
01 -72 dB
10 -78 dB
11 -84 dB
R/W
ACK
A7 A0
D0
ACK
D7
ACK
Start Stop CA6
CA0
1 1 1
( Note: Chip adrress: CA<6:0> = 35H, R/W =0.)
second byte: register address: A<7:0> = 02H
third byte: data D<7:0> = 30H
SDA
SCL
I 2 C Bus Control Register Write Example:
first byte: [CA R/W] = 6AH
Set channel 1L volume to 30H:
Example
1
first byte second byte third byte
75／148