Agilent N5161A/62A/81A/82A/83A MXG Signal Generators Service Guide
Troubleshooting
Overall Block Description
1-4
Synthesizer Circuitry
The frequency synthesis circuitry is based on a phase-locked loop (PLL). It uses a Frac-N synthesis FPGA to control the multiplier and
divider module. Frequency multipliers and dividers are used to extend the basic synthesis loop frequency range to cover 250 MHz to 6 GHz.
Frequency and phase modulation are built into the synthesizer circuitry using the Frac-N FPGA.
•
The VCO tunes over a range of 750 MHz to 1.5 GHz.
— From 250 MHz to 375 MHz, the VCO is divided by 4.
— From 375 MHz to 750 MHz, the VCO is divided by 2.
•
The PLL operates over a range of 1.5 to 3 GHz.
•
The heterodyne band provides frequencies from 100 kHz to 250 MHz and operates over a VCO range of 1.0001-1.25 GHz. The 100 kHz
to 250 MHz signal is obtained by mixing the heterodyne band with the 1 GHz LO signal provided by the reference circuitry. The
resultant IF signal is then amplified to provide the 100 kHz to 250 MHz RF signals.
Output Power Leveling Circuitry (Automatic Leveling Control Circuitry)
The Automatic Leveling Control (ALC) loop on the A3 RF assembly provides leveled output power. The ALC loop is a feedback control
system that monitors RF power and maintains power at a user-selected level. The RF path must provide a minimum power level to the ALC
loop for the ALC loop to work correctly. The minimum required power is slightly higher than the maximum-leveled power.
•
In closed loop mode, ALC on, a leveled output power is obtained by comparing a detected voltage with a reference voltage. The detected
voltage is generated by coupling off a portion of the RF output signal and converting it to a dc voltage using detector diodes. The
reference voltage is generated using calibrated DACs. When the reference and detected levels are not the same, the ALC integrator
output ramps up or down to increase or decrease the detected level. If the integrator cannot achieve a match between the detected and
reference voltages, an unleveled annunciator is displayed.
•
In open loop mode, ALC off, a leveled output power is obtained with a reference voltage. The reference voltage is used to control the
modulation drive current. The reference voltage is determined by setting the desired power. It includes the stored calibration data used to
compensate for any losses that occur after the detector.
All analog Amplitude Modulation (AM) is performed using a dedicated diode modulator in the ALC subsystem. For Pulse Modulation, ALC
is only on for a short period within the pulse duration. Outside this short period of time, ALC is in a holding state waiting for the next pulse.
A3 RF Assembly (N5183A Only)
NOTE
The N5183A A3 RF assembly is not interchangeable with the N5161A/62A/81A/82A A3 RF assembly.
The N5183A A3 RF assembly provides the circuitry to generate the frequency range of 100 kHz to 5 GHz and provides:
•
Frequency modulation
•
Amplitude modulation
•
Pulse modulation
•
Frequency accuracy
•
1 GHz LO signal to the heterodyne (HET) band mixer
•
Switching speed
•
Phase noise impairment
The A3 RF assembly also includes an ALC modulator and a pulse modulator for frequencies from
100 kHz to < 3.2 GHz.
Generating Frequencies
≤
3.2 GHz
The A3 RF assembly generates and modulates signals at frequencies from 100 kHz to
≤
3.2 GHz. The Mod Filter on the A7 Micro Deck
switches the RF signals to the main signal path. (The attenuator on the A7 Micro Deck impacts signal performance from 100 kHz to
≤
3.2 GHz. The high band coupler on the A7 Micro Deck impacts performance from < 2 GHz to
≤
3.2 GHz.)
Reference Circuitry
The reference circuitry uses a 10 MHz VCTCXO oscillator. The circuitry is designed to lock to an external reference frequency from 1 MHz
to 50 MHz, with a resolution of less than 0.1 Hz. Without the flexible reference option (Option 1ER), the reference will only lock to an
external reference of 10 MHz.
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