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MIC-3393 User Manual

Chapter 2

A

MI BIOS

Setup

2.2

Entering Setup

Turn on the computer, and there should be a POST (Power-On Self Test) screen that
shows the BIOS supporting the CPU. If there is no number assigned, please contact
an Advantech application engineer to obtain an up-to-date patch code file. This will
ensure that the CPU's system status is valid. After ensuring that you have a number
assigned to the patch code, press <DEL> and you will immediately be allowed to
enter Setup.

Figure 2.2 Press <DEL> to run setup

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Summary of Contents for MIC-3393

Page 1: ...User Manual MIC 3393 6U CompactPCI Intel Xeon Quad Dual Core Processor Blade...

Page 2: ...y as a consequence of such events Because of Advantech s high quality control standards and rigorous testing most of our customers never need to use our repair service If an Advantech product is defec...

Page 3: ...nce in which case the user will be required to correct the interference at his own expense FM This equipment has passed the FM certification According to the National Fire Pro tection Association work...

Page 4: ...to DB9 cable x1 Warranty certificate document x1 If any of these items are missing or damaged contact your distributor or sales repre sentative immediately Warning Warnings indicate potentially hazard...

Page 5: ...ur any liquid into an opening This may cause fire or electrical shock 13 Never open the equipment For safety reasons the equipment should be opened only by qualified service personnel 14 If one of the...

Page 6: ...ny components on the CPU card or other cards while the PC is on Disconnect power before making any configuration changes The sudden rush of power electrostatic discharge as you connect a jumper or ins...

Page 7: ...rdware Monitor 8 1 2 19 Super I O 8 1 2 20 RTC and Battery 8 1 2 21 IPMI 8 1 3 Functional Block Diagram 9 Figure 1 2 MIC 3393 functional block diagram 9 1 4 Jumpers and Switches 9 Table 1 6 MIC 3393 j...

Page 8: ...te assembly of MIC 3393C with MIC 3311 A2E 20 Figure 1 14Assemble MIC 3312 A1E 21 Figure 1 15Assemble MIC 3312 A2E 21 1 8 Battery Replacement 22 1 9 Software Support 22 Chapter 2 AMI BIOS Setup 23 2 1...

Page 9: ...anges and Exit 47 2 9 2 Discard Changes and Exit 47 2 9 3 Discard Changes 47 2 9 4 Load Optimal Defaults 47 2 9 5 Load Failsafe Defaults 48 Chapter 3 IPMI for the MIC 3393 49 3 1 Introduction 50 3 2 D...

Page 10: ...Connectors 62 Table A 5 CNSATA1 daughter board connector 62 Table A 6 CNSATA1 daughter board connector 62 A 5 1 M D PWR BMC HB and IDE Hot swap LEDs 62 Appendix B Programming the Watchdog Timer 63 B 1...

Page 11: ...Chapter 1 1 Hardware Configuration This chapter describes how to configure MIC 3393 hardware...

Page 12: ...TA disk drives and SATA RAID support of the ICH9R do not meet performance and reli ability requirements the RIO 3311 SAS version supports a 4 port SAS controller with RAID and failover support The MIC...

Page 13: ...on Technology and Intel Virtualization Technology The Intel 5100 MCH Chipset Intel ICH9R I O controller and coupled with the energy efficient technology found in Intel s 45nm silicon process enables i...

Page 14: ...ts can be selected in the BIOS menu These are mutually exclusive and can be set as LAN1 LAN2 of Front I O on the MIC 3393 LAN1 LAN2 LAN3 of Rear I O on the RTM PICMG 2 16 User can access LAN1 via fron...

Page 15: ...compliant ports are provided Two of them are routed to front panel connectors one is routed to an on board USB flash disk on the MIC 3393 The other four are routed to the RTM through the J3 connector...

Page 16: ...XTM for the MIC 3393B or the MIC 3393C two slot platform Extension modules are available with two options 1 2 14 Mechanical and Environmental Specifications Operating temperature 0 55 C 32 122 F Stora...

Page 17: ...parent PCI X to PCI bridge As a peripheral controller it allows the local MIC 3393 processor to configure and control the onboard local subsystem indepen dently from the CompactPCI bus host processor...

Page 18: ...ritical hardware parameters It is attached to the BMC to monitor the CPU temperature and core volt age information 1 2 19 Super I O The MIC 3393 Super I O device provides the following legacy PC devic...

Page 19: ...section carefully before changing the jumper and switch settings on your MIC 3393 board Table 1 6 MIC 3393 jumper descriptions Number Function JP7 Clear CMOS Table 1 7 MIC 3393 switch descriptions Nu...

Page 20: ...umper is used to erase CMOS data Follow the procedures below to clear the CMOS 1 Turn off the system 2 Close jumper JP7 1 2 for about 3 seconds 3 Set jumper JP7 back to normal 4 Turn on the system The...

Page 21: ...ting switch 2 and switch 4 to BMC Program mode Please refer to Table 1 12 for the setting of key 2 3 and 4 of SW4 1 Note represents the key Table 1 9 SW1 BMC Reset Button Platform Reset Button SW1 1 t...

Page 22: ...COM RTM COM1 COM2 ports selection for BMC SIO UART Default Front COM for BMC RTM COM1 for SIO COM1 RTM COM2 for SIO COM2 Front COM for SIO COM1 RTM COM1 for BMC RTM COM2 for SIO COM2 Front COM for SI...

Page 23: ...Selection Default XMC1 x8 or PMC x4 XMC2 x8 or PMC x4 XMC1 x8 or PMC x4 XMC2 2 x4 or PMC x4 XMC1 2 x4 or PMC x4 XMC2 x8 or PMC x4 XMC1 2 x4 or PMC x4 XMC2 2 x4 or PMC x4 Table 1 15 MIC 3393 connector...

Page 24: ...e USB interface can be disabled in the system BIOS setup The USB controller default is set to Enabled 1 5 2 Serial Ports The MIC 3393 provides one serial port and the RIO 3311 provides two serial port...

Page 25: ...em reset button resets all payload and application related circuitry It does not rest the system management IPMI related circuitry A separate BMC reset button on the front panel is provided for the BM...

Page 26: ...k on it Don t touch any components on the CPU board or other boards while the CompactPCI chassis is powered Disconnect power before making any configuration changes The sudden rush of power as you con...

Page 27: ...oard Installation Steps The MIC 3393 supports 2 5 SATA hard disk drive or CompactFlash Either of them is occupied the same location The SATA HDD daughter board is assembled on the MIC 3393 therefore i...

Page 28: ...M2 5 screw on the center of SATA HDD daughter board and four on the socket Figure 1 10 Loosen screws on the SATA HDD Daughter Board 2 Remove SATA HDD daughter board and socket Figure 1 11 Disassemble...

Page 29: ...n the CN2 connector of the CF daughter board to the CNSATA1 connector on the MIC 3393 Then fasten the four M2 5 8mm screws as shown circled in red in the picture below The screw circled in blue is use...

Page 30: ...rd Installation Steps The MIC 3393B and MIC 3393C support the MIC 3312 A1E and MIC 3312 A2E extension boards respectively Following steps illustrate the installation of the exten sion boards Figure 1...

Page 31: ...o the CNXTM1 connector on the MIC 3393 Then fasten the six M2 5 4mm screws in the locations circled in red in Figure 1 14 below for the MIC 3312 A1E or seven screws in the locations circled in red in...

Page 32: ...tech When ordering the battery please con tact your local Sales to check availability 1750129010 BATTERY 3V 210 mAh with WIRE ASS Y CR2032M1S8 LF 1 9 Software Support Windows XP Windows 2003 and Red H...

Page 33: ...Chapter 2 2 AMI BIOS Setup This chapter describes how to configure the AMI BIOS...

Page 34: ...ngs and control the special features of the MIC 3393 The Setup program uses a number of menus for making changes and turning the special features on or off This chapter describes the basic navigation...

Page 35: ...IOS supporting the CPU If there is no number assigned please contact an Advantech application engineer to obtain an up to date patch code file This will ensure that the CPU s system status is valid Af...

Page 36: ...an be configured Grayed out options cannot be configured whilst options in blue can The right frame displays the key legend Above the key legend is an area reserved for a text message When an option i...

Page 37: ...f the items in the left frame of the screen such as CPU Configuration to go to the sub menu for that item You can display an Advanced BIOS Setup option by highlighting it using the Arrow keys All Adva...

Page 38: ...tem It does this by creating virtual machines each running its own x86 operating system The default setting for this item is set to Enabled 2 4 1 2 PECI This item specifies the Platform Environment Co...

Page 39: ...m is set to Front 2 4 2 2 Select LAN2 mode Three options are available Front RTM or PICMG 2 16 Used to select LAN2 con nect to either RJ 45 LAN port on front panel RJ 45 LAN port on rear I O or backpl...

Page 40: ...tting is IDE 2 4 3 3 SATA 2 Configuration Two options are available Disabled or Enhanced The default setting is Enhanced 2 4 3 4 Primary Secondary Third Fourth IDE Master and Slave While entering setu...

Page 41: ...31 MIC 3393 User Manual Chapter 2 AMI BIOS Setup 2 4 4 Super I O Configuration Figure 2 8 Super I O configuration 2 4 4 1 Serial Port1 2 Address Used to select Serial Port1 Serial Port2 base addresses...

Page 42: ...er Manual 32 2 4 5 Hardware Health Configuration Figure 2 9 Hardware health configuration System temperature CPU temperature VTIN temperature and voltage status are displayed in the Hardware Health Co...

Page 43: ...ller Mode Configure the USB 2 0 controller in HiSpeed 480Mbps or FullSpeed 12Mbps The default setting for this item is set to HiSpeed 2 4 6 3 USB EHCI Hand Off This is a workaround for OS without EHCI...

Page 44: ...uts power management in the hands of the operating system The options for ACPI Aware O S are Yes or No in order to enable or disable ACPI support for the operating system The default setting is Yes 2...

Page 45: ...r disable Advanced Host Controller Interface AHCI support AHCI allows the storage driver to enable advanced Serial ATA features such as Native Command Queuing and hot plug The default setting is Enabl...

Page 46: ...MIC 3393 User Manual 36 2 4 9 Event Log Configuration Figure 2 14 Event log configuration 2 4 9 1 ECC Event Logging You can enable or disable ECC Event Logging The default setting is Enabled...

Page 47: ...MPS Configuration Figure 2 15 MPS configuration 2 4 10 1 MPS Revision MPS allows the BIOS to configure the Multi Processor Specification revision level Some operation systems will require revision 1...

Page 48: ...ng is 115200 8 n 1 2 4 11 4 Flow Control Select Flow Control for console redirection The default setting is None 2 4 11 5 Redirection after BIOS POST Three options are available Disabled Boot Loader o...

Page 49: ...2 17 Console re direction configuration 2 4 12 1 TCG TPM Support Enable or disable TPM TCG TPM 1 1 1 2 support in BIOS 2 4 12 2 Execute TPM Command Three options are available Don t change Disabled o...

Page 50: ...2 18 PCI PnP setup 2 5 1 Clear NVRAM Set this value to force the BIOS to clear the Non Volatile Random Access Memory NVRAM during system boot The default setting is No 2 5 2 Plug and Play O S Select N...

Page 51: ...IC 3393 User Manual Chapter 2 AMI BIOS Setup 2 6 Boot Setup Figure 2 19 Boot setup Note Hard Disk Drives will only appear on the setup screen when at least one hard disk drive is connected to the MIC...

Page 52: ...the time needed to boot the system The default set ting is on Enabled 2 6 1 2 Quiet Boot Used to display OEM logo when the setting is Enabled The default setting Dis abled displays normal POST messag...

Page 53: ...n Select Security Setup from the MIC 3393 Setup main BIOS setup menu All Security Setup options such as password protection and virus protection are described in this section To access the sub menu fo...

Page 54: ...MIC 3393 User Manual 44 2 8 Advanced Chipset Settings Figure 2 22 Advanced chipset settings...

Page 55: ...Dependent Sparing Enable or disable Channel dependent rank DIMM sparing 2 8 1 7 Channel 0 1 Enable or disable Channel 0 1 2 8 1 8 Channel Specific Sparing Enable or disable rank DIMM sparing feature...

Page 56: ...2 24 South Bridge chipset configuration 2 8 2 1 USB Functions The default setting is 12 USB Ports 2 8 2 2 USB Port Configure The default setting is 6X6 USB Ports 2 8 2 3 SMBUS Controller The default...

Page 57: ...making any permanent changes to the sys tem configuration 1 Select Exit Discarding Changes from the Exit menu and press Enter The fol lowing messages appear on the screen Discard Changes and Exit Setu...

Page 58: ...Manual 48 2 9 5 Load Failsafe Defaults This loads the basic defaults values for the MIC 3393 which may not work best for all computer applications Select Load Failsafe Defaults from the Exit menu and...

Page 59: ...Chapter 3 3 IPMI for the MIC 3393 This chapter describes IPMI con figuration for the MIC 3393...

Page 60: ...updating over serial port One hardware monitor One interrupt input Sensors threshold configuration Complete IPMI watchdog functionality reset power down power cycle Platform even filtering PEF and al...

Page 61: ...essaging interface channel connects the H8S 2167 s I2C inter face to the NIC s SMBus interface Table 3 1 Supported IPMI device global commands IPMI Device Global Commands NetFn Cmd Mandatory Optional...

Page 62: ...3 4 BMC device and messaging commands Table 3 5 BMC watchdog timer commands BMC Watchdog Timer Commands NetFn Cmd Mandatory Optional Reset Watchdog Timer App 0x22 M Set Watchdog Timer App 0x24 M Get W...

Page 63: ...NetFn Cmd Mandatory Optional Get SEL Info Storage Storage 0x40 M Reserve SEL Storage Storage 0x42 O Get SEL Entry Storage Storage 0x43 M Get SEL Time Storage Storage 0x48 M Set SEL Time Storage Storag...

Page 64: ...red status only N A 01h Hard Reset 02h Power Down 03h Power Cycle Power Failure 52h C0h 6Fh 00h Power Failure 00h Power Failure SEL Full 07h over 75 full N A 64h D0h 01h 09h over 90 full 0Bh 100 full...

Page 65: ...7 V N A 0x02 0x02 20h 01h 35 C 55 C 50 C N A N A N A N A 0x02 0x02 21h 01h 70 C N A 100 C N A N A N A N A 0x02 0x02 Table 3 13 Sensor device commands Sensor Device Command NetFn Cmd Mandatory Optional...

Page 66: ...ill then perform a graceful shutdown and light the blue LED whereas a non compliant OS will just shut down Note The Network function NetFn field identifies the functional class of the message The Netw...

Page 67: ...Appendix A A Pin Assignments This appendix describes pin assignments...

Page 68: ...GND 17 GND 3 3V IPMB_SCL IPMB_SDA GND PERR GND 16 GND DEVSEL GND V I O STOP LOCK GND 15 GND 3 3V FRAME IRDY BD_SEL TRDY GND 12 14 KEY AREA 11 GND AD 18 AD 17 AD 16 GND C BE 2 GND 10 GND AD 21 GND 3 3V...

Page 69: ...GND 14 GND AD 35 AD 34 AD 33 GND AD 32 GND 13 GND AD 38 GND V I O AD 37 AD 36 GND 12 GND AD 42 AD 41 AD 40 GND AD 39 GND 11 GND AD 45 GND V I O AD 44 AD 43 GND 10 GND AD 49 AD 48 AD 47 GND AD 46 GND...

Page 70: ...GND COM1_DCD COM1_RI COM2_CTS COM2_RX USB_OC6 GND 8 GND USB_OC9 USB_OC10 COM2_DSR TBD TMS USB_P6 GND 9 GND USB_P9 USB_P10 TBD TDI TBD TCK USB_P6 GND 10 GND USB_P9 USB_P10 TBD TDO TBD TRST USB_OC7 GND...

Page 71: ...NC NC XGI_TX_N0 GND 10 GND SATA_RX_P2 SATA_RX_P1 NC LAN3_SPEE D_1000 XGI_TX_P0 GND 11 GND GND GND LAN1_MDI0 LAN3_SPEE D_100 GND GND 12 GND SAS_RX_N3 SAS_TX_N3 LAN1_MDI0 LAN3_LNK ACT CLK_XGI GND 13 GND...

Page 72: ...TX_N0 11 NC 12 SATA_IRX_ DTX_P0 13 GND 14 GND 15 RSV 3 3V 16 5V 17 RSV 3 3V 18 5V 19 RSV 3 3V 20 5V Table A 6 CNSATA1 daughter board connector Name Description M D Green Indicates Master or Drone mode...

Page 73: ...Appendix B B Programming the Watchdog Timer This appendix describes how to program the watchdog timer...

Page 74: ...r by rewriting the I O port 443 and 043 hex while simultaneously setting it When you want to disable the watchdog timer your program should read I O port 043 hex The following example shows how you mi...

Page 75: ...Appendix C C FPGA This appendix describes FPGA configuration...

Page 76: ...blue LED during Hot Insert and Hot Remove The Drone Mode Unit is used to disable the CPCI bridge The other signals in the Miscellaneous Unit are for interfac ing with corresponding I O interface signa...

Page 77: ...Address Offset 0x04 H8 Address 0xFFC004 LPC Address na Bit Position Mnemonic Description R W Type Default 0x H8 LPC 7 1 Res Reserved RO RO 0 0 USB_FLASH _WP Write Protect for USB Flash USB FLASH disk...

Page 78: ...t Position Mnemonic Description R W Type Defaul t 0x H8 LPC 7 5 Res Reserved RO RO 3 h7 4 0 GA geographical address this register reflects the state of the GA 4 0 sig nals on board RO RO x Bit Positio...

Page 79: ...e 0 Bit D1 disabled FWH_SEL_ID can not be controlled by the value of D1 1 Bit D1 enabled FWH_SEL_ID can be controlled by the value of D1 RO RW 1 1 FWH_SEL_RE G FWH_SEL_ID control Current flash select...

Page 80: ...sition Mnemonic Description R W Type Default 0x H8 LPC 7 0 MIN_REV FPGA minor revision This register holds the minor revi sion ID Minor revision changes are small bug fixes and improvements which have...

Page 81: ...6H Name FWH_SEL_ID Address Offset 0x09 H8 Address 0xFFC009 LPC Address 0x446 Bit Position Mnemonic Description R W Type Default 0x H8 LPC 7 4 Res Reserved RO RO 0 3 BIOS_SWA P 0 IWD time out BIOS swap...

Page 82: ...FC008 LPC Address 0x443 Name WDG_disable Address Offset na H8 Address na LPC Address 0x444 Bit Position Mnemonic Description R W Type Default 0x H8 LPC 7 0 WDG watch dog timer value RO RW 0xFF Bit Pos...

Page 83: ...Appendix D D Glossary...

Page 84: ...t Output IC Integrated Circuit IMCH Integrated Memory Controller Hub LED Light Emitting Diode LPC Low Pin Count LV Low Voltage MAC Medium Access Control OS Operating System PCB Printed Wiring Board PC...

Page 85: ...75 MIC 3393 User Manual Appendix D Glossary...

Page 86: ...tions are subject to change without notice No part of this publication may be reproduced in any form or by any means electronic photocopying recording or otherwise without prior written permis sion of...

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