Advantech MIC-3393, User Manual

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67 MIC-3393 User Manual
Appendix C
F
PGA
C.2.2 General Control and Status Registers
This section describes functions of FPGA status and control registers, which are
related to the hardware. Additional registers which are not related to any internal
FPGA functions are listed in C.2.3.
Name:
CTRL
Address-Offset: 0x00
H8 Address: 0xFFC000
LPC Address: 0x441
Name: STAT
Address-Offset: 0x01
H8 Address: 0xFFC001
LPC Address: 0x442
Name: PRESENT
Address-Offset: 0x04
H8 Address: 0xFFC004
LPC Address: na
Bit Position Mnemonic Description
R/W (Type)
Default
0x
H8 LPC
7 : 1 Res Reserved RO RO 0
0
USB_FLASH
_WP
Write Protect for USB Flash USB
FLASH disk write protected, Logic
'1' for write protection
RO RW 0
Bit Position Mnemonic Description
R/W (Type)
Default
0x
H8 LPC
7 : 4 UART_MUX
Reflects the state of the UART multi-
plexer DIP switches
RO RO x
3 SLPS5
System in Sleep State S5 : '1'
means in SLPS5
RO RO x
Bit Position Mnemonic Description
R/W (Type)
Default
0x
H8 LPC
7 : 2 Res Reserved RO na 0
1 XTM_PRES XTM connected : '1' = XTM present RO na x
0 RTM_PRES
RTM connected : '1' = RTM
present
RO na x